Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19405

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3068

1

T5

7

T12

1

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16145

1

T2

20

T3

14

T4

20

auto[1]

6328

1

T5

7

T9

1

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	606	1			T53	8		T41	1		T48	1
values[0]	91	1			T95	17		T258	23		T297	26
values[1]	603	1			T53	10		T144	1		T62	19
values[2]	2850	1			T18	16		T20	17		T38	2
values[3]	664	1			T5	7		T9	1		T16	1
values[4]	688	1			T12	1		T19	4		T47	25
values[5]	798	1			T15	12		T40	6		T129	3
values[6]	798	1			T14	24		T128	1		T61	28
values[7]	768	1			T61	11		T62	3		T153	23
values[8]	574	1			T46	3		T42	1		T175	11
values[9]	789	1			T13	5		T15	13		T62	23
minimum	13244	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	588	1			T62	19		T230	14		T96	8
values[1]	2908	1			T18	16		T20	17		T38	2
values[2]	603	1			T5	7		T9	1		T16	1
values[3]	789	1			T12	1		T19	4		T47	25
values[4]	844	1			T14	24		T15	12		T40	6
values[5]	782	1			T128	1		T205	4		T225	2
values[6]	646	1			T61	11		T42	1		T62	3
values[7]	567	1			T46	3		T175	11		T145	12
values[8]	863	1			T13	5		T15	13		T53	8
values[9]	76	1			T170	1		T237	23		T197	17
minimum	13807	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T62	9		T230	1		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T96	8		T182	2		T251	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T18	16		T20	2		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	7		T264	1		T156	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	1		T46	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	5		T16	1		T17	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T205	1		T222	6		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T19	3		T47	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T40	4		T129	1		T61	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	12		T15	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T128	1		T205	4		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T250	11		T134	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T61	6		T42	1		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T62	2		T153	12		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	3		T142	5		T225	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T175	11		T145	12		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	4		T15	1		T152	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T53	8		T62	13		T231	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T170	1		T197	9		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T237	13		T300	10		T347	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13537	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T144	1		T94	1		T95	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T62	10		T230	13		T233	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T296	1		T238	7		T268	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T20	15		T39	14		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T156	8		T158	9		T238	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T46	4		T129	11		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T5	2		T141	16		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T239	1		T273	6		T196	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	1		T47	12		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T40	2		T129	2		T61	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	12		T15	11		T150	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T225	1		T166	17		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T250	11		T134	12		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T61	5		T98	11		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T62	1		T153	11		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	15		T225	19		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T167	5		T131	2		T273	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T15	12		T152	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T62	10		T232	1		T146	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T197	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T237	10		T348	10		T306	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T95	8		T299	2		T183	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T41	1		T48	1		T49	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T53	8		T231	11		T146	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T258	12		T297	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T95	9		T349	1		T331	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T53	10		T62	9		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	1		T94	1		T96	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T18	16		T20	2		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T53	7		T264	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	1		T46	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	5		T16	1		T17	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T205	1		T130	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T12	1		T19	3		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	4		T129	1		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	1		T226	10		T225	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T128	1		T61	15		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	12		T150	1		T43	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T61	6		T205	4		T154	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T62	2		T153	12		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T46	3		T42	1		T98	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T175	11		T164	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	4		T15	1		T152	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T62	13		T145	12		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13128	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T198	14		T336	1		T350	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T146	21		T255	10		T237	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T258	11		T297	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T95	8		T349	9		T331	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T62	10		T230	13		T250	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T238	7		T299	2		T268	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T20	15		T39	14		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T296	1		T158	9		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T46	4		T129	11		T150	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T5	2		T27	1		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T239	1		T273	6		T196	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T19	1		T47	12		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T40	2		T129	2		T143	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	11		T225	6		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T61	13		T225	1		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	12		T150	3		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T61	5		T166	17		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T62	1		T153	11		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T98	11		T142	15		T225	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T167	5		T131	2		T239	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T15	12		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T62	10		T232	1		T29	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T62	11		T230	14		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T96	1		T182	2		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T18	2		T20	17		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	1		T264	1		T156	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T46	5		T129	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	6		T16	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T205	1		T222	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T19	3		T47	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	5		T129	3		T61	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	13		T15	12		T150	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T128	1		T205	1		T225	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T250	12		T134	13		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T61	6		T42	1		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T62	2		T153	12		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	1		T142	16		T225	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T175	1		T145	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	4		T15	13		T152	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T53	1		T62	11		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T170	1		T197	9		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T237	11		T300	1		T347	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13662	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T144	1		T94	1		T95	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T62	8		T233	15		T258	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T96	7		T251	18		T296	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T18	14		T45	16		T93	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T53	6		T156	7		T158	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	1		T177	1		T227	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	1		T17	8		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T222	5		T273	14		T253	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T19	1		T47	12		T235	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T40	1		T61	14		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	11		T43	2		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T205	3		T154	6		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T250	10		T148	8		T228	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T61	5		T98	11		T154	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T62	1		T153	11		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	2		T142	4		T225	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T175	10		T145	11		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	1		T152	17		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T53	7		T62	12		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T197	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T237	12		T300	9		T348	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T53	9		T156	8		T267	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T95	8		T183	14		T351	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T41	1		T48	1		T49	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T53	1		T231	1		T146	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T258	12		T297	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T95	9		T349	10		T331	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T53	1		T62	11		T230	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T144	1		T94	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T18	2		T20	17		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	1		T264	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	1		T46	5		T129	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	6		T16	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T205	1		T130	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T19	3		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	5		T129	3		T143	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T15	12		T226	1		T225	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T128	1		T61	14		T225	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	13		T150	4		T43	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T61	6		T205	1		T154	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	2		T153	12		T134	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	1		T42	1		T98	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T175	1		T164	1		T167	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	4		T15	13		T152	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T62	11		T145	1		T232	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13244	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T198	2		T185	8		T321	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T53	7		T231	10		T146	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T258	11		T297	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T95	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T53	9		T62	8		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T96	7		T251	18		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T18	14		T45	16		T93	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T53	6		T296	13		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	1		T177	1		T227	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T17	8		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T273	14		T253	15		T201	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T19	1		T47	12		T253	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	1		T143	10		T222	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T226	9		T225	7		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T61	14		T239	3		T178	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	11		T43	2		T250	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T61	5		T205	3		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T62	1		T153	11		T294	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	2		T98	11		T142	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T175	10		T252	11		T239	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T152	17		T197	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T62	12		T145	11		T252	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11