Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T131	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T261	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T142	5		T269	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T37	1		T262	15		T270	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T62	2		T205	1		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T61	15		T144	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T46	4		T205	4		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	5		T167	1		T239	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T246	1		T136	1		T271	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	1		T47	13		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	1		T19	3		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T264	1		T152	18		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T9	1		T18	16		T20	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T144	1		T232	1		T154	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	5		T129	1		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T230	1		T231	11		T176	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	4		T150	1		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	4		T17	9		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T53	10		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	1		T128	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T129	1		T182	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T14	12		T53	8		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T142	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T262	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T62	1		T234	12		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T61	13		T94	10		T95	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	4		T26	1		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T27	1		T167	5		T239	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	12		T271	14		T259	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T47	12		T236	2		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	11		T19	1		T143	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T152	14		T131	2		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T20	15		T39	14		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T232	1		T134	10		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	2		T129	11		T61	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T230	13		T167	7		T228	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	2		T150	15		T166	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T254	11		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T150	3		T167	11		T246	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	12		T225	19		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T129	2		T225	1		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T14	12		T150	12		T141	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T46	6		T62	2		T205	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T61	14		T144	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T205	1		T26	4		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	1		T94	11		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	12		T19	3		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T47	13		T152	15		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T18	2		T20	17		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T264	1		T263	1		T131	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T129	12		T62	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T144	1		T230	14		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	6		T61	6		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T144	1		T25	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T40	5		T150	16		T166	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	4		T17	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T150	4		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	13		T15	13		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T129	3		T53	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T150	13		T141	17		T62	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T225	2		T131	1		T265	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T53	1		T157	8		T194	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	2		T62	1		T142	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T61	14		T95	8		T225	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T205	3		T26	1		T272	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	1		T251	18		T233	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T19	1		T149	11		T273	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	12		T152	17		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T18	14		T45	16		T93	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T238	9		T241	15		T274	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T62	12		T43	2		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T231	10		T154	15		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T61	5		T53	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T176	11		T201	15		T275	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	1		T166	14		T273	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T17	8		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T157	9		T160	9		T276	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	11		T225	17		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T53	9		T250	10		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T62	8		T153	11		T96	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T277	14		T86	8		T278	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T53	7		T157	8		T268	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T131	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T142	16		T269	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T37	1		T262	16		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T62	2		T205	1		T234	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T61	14		T144	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T46	6		T205	1		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T27	5		T167	6		T239	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T246	1		T136	13		T271	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T47	13		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	12		T19	3		T143	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T264	1		T152	15		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T9	1		T18	2		T20	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T144	1		T232	2		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	6		T129	12		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T230	14		T231	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T40	5		T150	16		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	4		T17	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T53	1		T150	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	13		T128	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T129	3		T182	1		T225	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T14	13		T53	1		T150	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T261	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T142	4		T269	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T262	14		T270	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T62	1		T156	7		T255	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T61	14		T95	8		T225	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T46	2		T205	3		T26	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T27	1		T239	2		T233	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T271	11		T259	14		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	12		T251	18		T252	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	1		T143	10		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T152	17		T235	1		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T18	14		T45	16		T62	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T154	9		T158	13		T279	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T61	5		T53	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T231	10		T176	11		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	1		T166	14		T273	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	1		T17	8		T254	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	9		T238	7		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	11		T225	17		T148	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T250	10		T156	8		T157	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T14	11		T53	7		T62	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11