Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19162

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T5

7

T12

1

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16655

1

T2

20

T3

14

T4

20

auto[1]

5818

1

T5

7

T9

1

T12

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T280	15		T281	9		-	-
values[0]	54	1			T53	7		T245	4		T203	9
values[1]	617	1			T9	1		T46	5		T129	3
values[2]	3143	1			T12	1		T16	1		T18	16
values[3]	436	1			T19	4		T141	17		T205	4
values[4]	631	1			T5	7		T144	1		T145	12
values[5]	629	1			T15	12		T128	1		T40	6
values[6]	672	1			T144	1		T153	23		T43	8
values[7]	651	1			T13	5		T61	11		T53	8
values[8]	657	1			T47	25		T61	28		T150	4
values[9]	1358	1			T14	24		T15	13		T17	9
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T9	1		T12	1		T46	5
values[1]	3074	1			T16	1		T18	16		T19	4
values[2]	607	1			T205	4		T167	18		T222	6
values[3]	551	1			T5	7		T15	12		T128	1
values[4]	613	1			T40	6		T129	12		T150	13
values[5]	589	1			T150	16		T144	1		T231	11
values[6]	835	1			T13	5		T47	25		T61	39
values[7]	517	1			T150	4		T94	12		T182	1
values[8]	1109	1			T14	24		T15	13		T17	9
values[9]	161	1			T62	23		T96	8		T146	41
minimum	13619	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	1		T46	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T264	1		T226	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T16	1		T18	16		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T176	12		T142	5		T239	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T205	4		T167	1		T252	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T167	1		T222	6		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	1		T145	12		T154	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	5		T128	1		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	1		T150	1		T152	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	4		T43	6		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T150	1		T144	1		T26	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T231	11		T29	2		T156	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	4		T47	13		T53	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T61	21		T222	16		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T150	1		T94	2		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T164	1		T131	1		T148	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T15	1		T17	9		T62	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T14	12		T53	10		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T96	8		T198	3		T259	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T62	13		T146	20		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13496	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	4		T129	2		T225	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T225	19		T177	9		T273	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1122	1			T19	1		T20	15		T39	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T142	15		T254	14		T267	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T167	5		T236	2		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T167	11		T131	2		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	11		T239	1		T158	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	2		T179	11		T283	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T129	11		T150	12		T152	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	2		T43	2		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	15		T26	1		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	1		T156	11		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	1		T47	12		T62	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T61	18		T237	10		T159	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T150	3		T94	10		T143	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T148	10		T234	12		T239	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T15	12		T62	10		T232	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	12		T230	13		T166	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T198	14		T160	1		T284	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T62	10		T146	21		T134	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	2		T12	1		T13	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T281	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T53	7		T203	4		T285	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T245	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T46	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T264	1		T226	10		T177	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T16	1		T18	16		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T176	12		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T19	3		T141	1		T205	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T222	6		T252	12		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T145	12		T154	10		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	5		T144	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T129	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T128	1		T40	4		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T144	1		T153	12		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	6		T231	11		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	4		T53	8		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T61	6		T222	16		T282	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	13		T150	1		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T61	15		T42	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T15	1		T17	9		T62	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T14	12		T53	10		T62	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T281	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T280	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T203	5		T285	1		T286	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T46	4		T129	2		T225	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T177	9		T273	6		T196	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T20	15		T39	14		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T142	15		T225	19		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T19	1		T141	16		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T250	1		T235	1		T254	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T30	1		T239	1		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	2		T131	2		T238	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	11		T129	11		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	2		T131	13		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T153	11		T26	1		T225	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T43	2		T246	14		T157	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T150	15		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T61	5		T29	1		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T47	12		T150	3		T62	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T61	13		T248	25		T276	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T15	12		T62	10		T232	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T14	12		T62	10		T230	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T46	5		T129	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T264	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T16	1		T18	2		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T176	1		T142	16		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T205	1		T167	6		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T167	12		T222	1		T131	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	12		T145	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	6		T128	1		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	12		T150	13		T152	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	5		T43	6		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T150	16		T144	1		T26	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T231	1		T29	3		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T13	4		T47	13		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T61	20		T222	1		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T150	4		T94	12		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T164	1		T131	1		T148	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T15	13		T17	1		T62	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T14	13		T53	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T96	1		T198	15		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T62	11		T146	22		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13614	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T53	6		T251	18		T157	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T226	9		T225	17		T177	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T18	14		T19	1		T45	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T176	11		T142	4		T239	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T205	3		T252	12		T253	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T222	5		T252	11		T235	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	11		T154	9		T158	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T5	1		T238	7		T283	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	17		T255	14		T273	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	1		T43	2		T154	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T26	1		T225	7		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T231	10		T156	3		T271	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T47	12		T53	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	19		T222	15		T237	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T143	10		T27	1		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T148	8		T239	2		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T17	8		T62	8		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T14	11		T53	9		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T96	7		T198	2		T259	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T62	12		T146	19		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T203	3		T287	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T281	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T280	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T53	1		T203	6		T285	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T245	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T46	5		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T264	1		T226	1		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1443	1			T16	1		T18	2		T20	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T176	1		T142	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T19	3		T141	17		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T222	1		T252	1		T250	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T145	1		T154	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	6		T144	1		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	12		T129	12		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T128	1		T40	5		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T144	1		T153	12		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	6		T231	1		T246	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	4		T53	1		T150	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T61	6		T222	1		T282	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T47	13		T150	4		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T61	14		T42	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T15	13		T17	1		T62	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T14	13		T53	1		T62	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T53	6		T203	3		T286	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T157	9		T197	8		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T226	9		T177	1		T273	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T18	14		T45	16		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T176	11		T142	4		T225	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T19	1		T205	3		T252	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T222	5		T252	11		T235	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T145	11		T154	9		T158	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T180	8		T288	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	17		T255	14		T273	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T40	1		T154	6		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	11		T26	1		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T43	2		T231	10		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	1		T53	7		T175	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T61	5		T222	15		T156	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T47	12		T62	1		T143	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T61	14		T248	25		T276	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T17	8		T62	8		T96	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T14	11		T53	9		T62	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11