Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19204

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3269

1

T12

1

T13

5

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16710

1

T2

20

T3

14

T4

20

auto[1]

5763

1

T5

7

T12

1

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T199	1		T84	1		T280	11
values[0]	26	1			T289	5		T290	8		T291	13
values[1]	681	1			T17	9		T150	16		T141	17
values[2]	528	1			T264	1		T205	1		T263	1
values[3]	631	1			T62	19		T230	14		T98	23
values[4]	3109	1			T12	1		T14	24		T15	13
values[5]	631	1			T129	12		T150	13		T144	1
values[6]	773	1			T13	5		T19	4		T128	1
values[7]	599	1			T9	1		T47	25		T61	28
values[8]	658	1			T5	7		T46	3		T61	11
values[9]	1223	1			T15	12		T16	1		T40	6
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T17	9		T150	16		T141	17
values[1]	515	1			T252	12		T250	2		T246	1
values[2]	715	1			T12	1		T62	19		T230	14
values[3]	3074	1			T14	24		T15	13		T18	16
values[4]	670	1			T129	3		T53	8		T150	13
values[5]	664	1			T13	5		T19	4		T61	28
values[6]	621	1			T5	7		T128	1		T47	25
values[7]	733	1			T9	1		T15	12		T61	11
values[8]	924	1			T16	1		T40	6		T46	8
values[9]	147	1			T25	1		T166	32		T133	2
minimum	13603	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T150	1		T141	1		T62	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T17	9		T250	11		T227	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T250	1		T149	12		T255	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T252	12		T246	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T230	1		T231	11		T154	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	1		T62	9		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T15	1		T18	16		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	12		T144	1		T176	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	8		T150	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T129	1		T133	1		T157	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T61	15		T53	7		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	4		T19	3		T62	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	5		T128	1		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T42	1		T95	9		T142	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T15	1		T61	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	1		T152	18		T146	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T16	1		T150	1		T175	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T40	4		T46	4		T26	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T133	1		T292	5		T224	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T25	1		T166	15		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T150	15		T141	16		T62	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T250	11		T227	14		T157	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T250	1		T149	6		T255	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T149	6		T265	2		T276	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T230	13		T167	18		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T62	10		T94	10		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T15	12		T20	15		T39	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	12		T143	6		T156	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T150	12		T167	5		T234	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T129	2		T157	2		T279	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T61	13		T27	1		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T19	1		T62	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	2		T47	12		T225	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T95	8		T142	15		T225	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	11		T61	5		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T152	14		T146	21		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T150	3		T153	11		T225	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	2		T46	4		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T292	1		T224	7		T293	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T166	17		T149	11		T254	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T199	1		T84	1		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T289	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T290	3		T291	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T150	1		T141	1		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T17	9		T149	1		T157	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T264	1		T205	1		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T252	12		T250	11		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T230	1		T167	2		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T62	9		T98	12		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T15	1		T18	16		T20	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T14	12		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T129	1		T150	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	11		T131	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T128	1		T167	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	4		T19	3		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	1		T47	13		T61	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T42	1		T62	13		T152	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	5		T61	6		T96	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	3		T144	1		T156	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T15	1		T16	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T40	4		T46	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T280	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T290	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	15		T141	16		T62	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	6		T157	7		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T250	1		T149	6		T271	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T250	11		T227	14		T241	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T230	13		T167	18		T134	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T62	10		T98	11		T232	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T15	12		T20	15		T39	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	12		T94	10		T156	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T129	11		T150	12		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T143	6		T156	11		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T167	5		T131	13		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	1		T19	1		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T47	12		T61	13		T225	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T62	10		T152	14		T95	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	2		T61	5		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T156	8		T227	1		T237	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T15	11		T150	3		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T40	2		T46	4		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T150	16		T141	17		T62	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	1		T250	12		T227	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T250	2		T149	7		T255	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T252	1		T246	1		T149	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T230	14		T231	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	1		T62	11		T94	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T15	13		T18	2		T20	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	13		T144	1		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T53	1		T150	13		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T129	3		T133	1		T157	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T61	14		T53	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	4		T19	3		T62	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	6		T128	1		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T42	1		T95	9		T142	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	1		T15	12		T61	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T144	1		T152	15		T146	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T16	1		T150	4		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	5		T46	6		T26	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T133	1		T292	4		T224	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T25	1		T166	18		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T290	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T62	1		T205	3		T154	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T17	8		T250	10		T227	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T149	11		T255	14		T271	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T252	11		T276	14		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T231	10		T154	6		T254	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T62	8		T98	11		T222	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T18	14		T45	16		T53	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	11		T176	11		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T53	7		T273	14		T294	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T157	9		T279	4		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T61	14		T53	6		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	1		T19	1		T62	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T47	12		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T95	8		T142	4		T225	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T61	5		T96	7		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	17		T146	19		T156	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T175	10		T153	11		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	1		T46	2		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T292	2		T224	2		T295	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T166	14		T149	12		T254	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T199	1		T84	1		T280	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T289	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T290	6		T291	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T150	16		T141	17		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	1		T149	7		T157	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T264	1		T205	1		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T252	1		T250	12		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T230	14		T167	20		T134	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T62	11		T98	12		T232	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T15	13		T18	2		T20	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T14	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T129	12		T150	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T143	7		T131	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T128	1		T167	6		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	4		T19	3		T129	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	1		T47	13		T61	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T42	1		T62	11		T152	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	6		T61	6		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T46	1		T144	1		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T15	12		T16	1		T150	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T40	5		T46	5		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T290	2		T291	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T62	1		T205	3		T251	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T17	8		T157	8		T238	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T154	9		T149	11		T271	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T252	11		T250	10		T227	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T255	14		T276	16		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	8		T98	11		T222	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T18	14		T45	16		T53	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	11		T176	11		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T229	8		T294	1		T253	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	10		T156	3		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T296	13		T273	14		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	1		T19	1		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T47	12		T61	14		T53	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T62	12		T152	17		T95	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T61	5		T96	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	2		T156	7		T237	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T175	10		T153	11		T226	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T40	1		T26	1		T146	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11