Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19222

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3251

1

T13

5

T14

24

T15

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16686

1

T2

20

T3

14

T4

20

auto[1]

5787

1

T9

1

T14

24

T15

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	219	1			T150	13		T141	17		T62	19
values[0]	11	1			T270	11		-	-		-	-
values[1]	684	1			T46	5		T144	1		T42	1
values[2]	664	1			T46	3		T61	28		T205	4
values[3]	583	1			T16	1		T47	25		T152	32
values[4]	728	1			T15	12		T19	4		T264	1
values[5]	2903	1			T9	1		T18	16		T20	17
values[6]	775	1			T5	7		T129	12		T61	11
values[7]	642	1			T13	5		T17	9		T40	6
values[8]	730	1			T12	1		T15	13		T128	1
values[9]	933	1			T14	24		T129	3		T53	18
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	655	1			T46	5		T42	1		T94	11
values[1]	631	1			T16	1		T46	3		T61	28
values[2]	663	1			T15	12		T47	25		T152	32
values[3]	3000	1			T18	16		T19	4		T20	17
values[4]	527	1			T9	1		T129	12		T144	1
values[5]	771	1			T5	7		T61	11		T53	7
values[6]	757	1			T13	5		T17	9		T40	6
values[7]	672	1			T12	1		T14	24		T15	13
values[8]	923	1			T129	3		T53	10		T150	13
values[9]	70	1			T53	8		T225	2		T131	1
minimum	13804	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	1		T142	5		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T42	1		T94	1		T95	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	3		T205	4		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	1		T61	15		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	1		T252	3		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	13		T152	18		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T18	16		T19	3		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T264	1		T263	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T129	1		T62	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T144	1		T232	1		T154	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	5		T61	6		T53	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T230	1		T182	1		T176	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T40	4		T150	1		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	4		T17	9		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T128	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	12		T15	1		T225	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T129	1		T53	10		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T150	1		T141	1		T62	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T131	1		T86	9		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T53	8		T225	1		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13557	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T144	1		T158	5		T254	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	4		T142	15		T134	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T94	10		T95	8		T225	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	1		T248	7		T201	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T61	13		T27	1		T167	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	11		T273	5		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	12		T152	14		T236	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T19	1		T20	15		T39	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T131	2		T238	7		T266	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T129	11		T62	10		T143	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T232	1		T149	11		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	2		T61	5		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T230	13		T146	21		T167	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	2		T150	15		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	1		T273	6		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T150	3		T167	11		T246	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	12		T15	12		T225	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T129	2		T153	11		T250	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T150	12		T141	16		T62	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T86	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	1		T194	12		T88	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T158	6		T254	10		T301	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T201	5		T180	2		T302	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T150	1		T141	1		T62	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T270	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T46	1		T62	2		T205	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T144	1		T42	1		T94	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	3		T205	4		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	15		T27	5		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T252	3		T246	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	1		T47	13		T152	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	1		T19	3		T282	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T264	1		T263	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T9	1		T18	16		T20	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T144	1		T232	1		T154	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	5		T129	1		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T230	1		T182	1		T176	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	4		T150	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	4		T17	9		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T128	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T225	18		T148	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T129	1		T53	10		T153	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T14	12		T53	8		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T201	2		T180	6		T302	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T150	12		T141	16		T62	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	4		T62	1		T142	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T94	10		T95	8		T225	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T26	1		T134	12		T198	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T61	13		T27	1		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	12		T271	14		T258	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	12		T152	14		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	11		T19	1		T227	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T131	2		T149	6		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T20	15		T39	14		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T232	1		T149	11		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	2		T129	11		T61	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T230	13		T146	21		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	2		T150	15		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	1		T273	6		T254	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T150	3		T166	17		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	12		T225	19		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T129	2		T153	11		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	12		T225	1		T229	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	5		T142	16		T134	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	1		T94	11		T95	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T46	1		T205	1		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	1		T61	14		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	12		T252	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	13		T152	15		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T18	2		T19	3		T20	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T264	1		T263	1		T131	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	1		T129	12		T62	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T144	1		T232	2		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	6		T61	6		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T230	14		T182	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T40	5		T150	16		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	4		T17	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T128	1		T150	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	13		T15	13		T225	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T129	3		T53	1		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T150	13		T141	17		T62	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T131	1		T86	9		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T53	1		T225	2		T194	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13649	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T144	1		T158	7		T254	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	4		T156	7		T255	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T95	8		T225	7		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T46	2		T205	3		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T61	14		T27	1		T251	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T252	2		T273	10		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T47	12		T152	17		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T18	14		T19	1		T45	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T238	9		T241	15		T260	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T62	12		T226	9		T231	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T154	15		T149	12		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T61	5		T53	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T176	11		T146	19		T228	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T40	1		T145	11		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	1		T17	8		T273	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T157	9		T276	16		T303	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	11		T225	17		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T53	9		T153	11		T250	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T62	8		T96	7		T229	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T86	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T53	7		T304	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T62	1		T158	10		T262	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T158	4		T254	14		T301	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T201	3		T180	7		T302	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T150	13		T141	17		T62	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	5		T62	2		T205	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T144	1		T42	1		T94	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T46	1		T205	1		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T61	14		T27	5		T167	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T252	1		T246	1		T136	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	1		T47	13		T152	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	12		T19	3		T282	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T264	1		T263	1		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T9	1		T18	2		T20	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T144	1		T232	2		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	6		T129	12		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T230	14		T182	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	5		T150	16		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	4		T17	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T128	1		T150	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	13		T225	20		T148	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T129	3		T53	1		T153	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	13		T53	1		T225	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T201	4		T180	1		T305	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T62	8		T96	7		T252	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T270	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T62	1		T142	4		T156	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T95	8		T225	7		T222	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	2		T205	3		T26	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	14		T27	1		T233	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T252	2		T271	11		T258	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T47	12		T152	17		T251	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T19	1		T227	19		T273	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T149	11		T296	13		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T18	14		T45	16		T62	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T154	9		T149	12		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T61	5		T53	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T176	11		T146	19		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	1		T233	3		T258	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T17	8		T273	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T145	11		T166	14		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T225	17		T148	8		T160	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T53	9		T153	11		T250	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	11		T53	7		T229	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11