Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19121

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3352

1

T9

1

T12

1

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16690

1

T2

20

T3

14

T4

20

auto[1]

5783

1

T5

7

T13

5

T15

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T62	23		T306	9		-	-
values[0]	62	1			T167	6		T275	3		T274	15
values[1]	702	1			T62	3		T152	32		T230	14
values[2]	571	1			T144	1		T42	1		T232	2
values[3]	636	1			T15	13		T17	9		T46	5
values[4]	490	1			T12	1		T264	1		T167	12
values[5]	846	1			T46	3		T144	1		T205	4
values[6]	656	1			T128	1		T150	4		T231	11
values[7]	815	1			T9	1		T13	5		T15	12
values[8]	732	1			T5	7		T14	24		T16	1
values[9]	3330	1			T18	16		T20	17		T38	2
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	791	1			T62	3		T152	32		T230	14
values[1]	569	1			T46	5		T144	1		T42	1
values[2]	751	1			T15	13		T61	11		T144	1
values[3]	516	1			T12	1		T17	9		T46	3
values[4]	835	1			T150	4		T144	1		T264	1
values[5]	697	1			T15	12		T128	1		T62	19
values[6]	3038	1			T9	1		T13	5		T16	1
values[7]	712	1			T5	7		T14	24		T19	4
values[8]	837	1			T129	3		T47	25		T53	8
values[9]	99	1			T258	23		T266	1		T202	1
minimum	13628	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T62	2		T152	18		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T176	12		T146	20		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	1		T144	1		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T42	1		T225	18		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T61	6		T144	1		T182	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	1		T205	1		T95	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T17	9		T46	3		T255	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	1		T167	1		T177	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T150	1		T144	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T94	1		T98	12		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	1		T231	11		T154	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T128	1		T62	9		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T13	4		T18	16		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	1		T16	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	5		T53	7		T252	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	12		T19	3		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T129	1		T47	13		T62	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T53	8		T27	5		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T266	1		T180	2		T307	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T258	12		T202	1		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13506	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T62	1		T152	14		T230	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T146	21		T131	2		T246	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T46	4		T232	1		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T225	19		T166	17		T131	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T61	5		T225	1		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	12		T95	8		T296	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T255	10		T157	7		T196	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T167	11		T177	9		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T150	3		T229	2		T250	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T94	10		T98	11		T239	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	11		T158	9		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	10		T153	11		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T13	1		T20	15		T39	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	2		T150	12		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T236	2		T227	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	12		T19	1		T129	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T129	2		T47	12		T62	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T27	1		T167	7		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T180	6		T307	10		T305	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T258	11		T306	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	2		T12	1		T13	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T62	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T167	1		T275	3		T309	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T274	8		T283	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T62	2		T152	18		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	20		T131	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T144	1		T232	1		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T42	1		T176	12		T225	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T17	9		T46	1		T61	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T205	1		T95	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T264	1		T132	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T167	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T46	3		T144	1		T205	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T94	1		T98	12		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T150	1		T231	11		T154	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T128	1		T145	12		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	4		T15	1		T61	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T150	1		T62	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	5		T53	7		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	12		T16	1		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T18	16		T20	2		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T129	1		T53	8		T27	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T62	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T306	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T167	5		T309	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T274	7		T283	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T62	1		T152	14		T230	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	21		T131	2		T246	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T232	1		T26	1		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T225	19		T166	17		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	4		T61	5		T225	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	12		T95	8		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T134	12		T196	9		T253	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T167	11		T159	13		T276	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T250	5		T255	10		T157	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T94	10		T98	11		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T150	3		T229	2		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T234	12		T149	11		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T15	11		T61	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T150	12		T62	10		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	2		T141	16		T236	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	12		T19	1		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T20	15		T39	14		T129	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T129	11		T27	1		T167	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T62	2		T152	15		T230	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T176	1		T146	22		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	5		T144	1		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	1		T225	20		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T61	6		T144	1		T182	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	13		T205	1		T95	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	1		T46	1		T255	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T167	12		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T150	4		T144	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T94	11		T98	12		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	12		T231	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T128	1		T62	11		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T13	4		T18	2		T20	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T16	1		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	6		T53	1		T252	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	13		T19	3		T129	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T129	3		T47	13		T62	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	1		T27	5		T167	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T266	1		T180	7		T307	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T258	12		T202	1		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13609	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T62	1		T152	17		T43	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T176	11		T146	19		T148	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T26	1		T239	3		T244	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T225	17		T154	9		T166	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T61	5		T252	2		T156	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T95	8		T296	13		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T17	8		T46	2		T255	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T177	1		T157	9		T259	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T205	3		T96	7		T229	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T98	11		T145	11		T222	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T231	10		T154	6		T158	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T62	8		T153	11		T222	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T13	1		T18	14		T45	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T40	1		T175	10		T226	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T53	6		T252	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	11		T19	1		T53	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T47	12		T62	12		T143	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	7		T27	1		T156	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T180	1		T307	10		T305	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T258	11		T310	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T270	10		T309	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T62	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T306	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T167	6		T275	1		T309	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T274	8		T283	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T62	2		T152	15		T230	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T146	22		T131	3		T246	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	1		T232	2		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	1		T176	1		T225	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	1		T46	5		T61	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	13		T205	1		T95	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T264	1		T132	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	1		T167	12		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T46	1		T144	1		T205	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T94	11		T98	12		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T150	4		T231	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	1		T145	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	4		T15	12		T61	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T9	1		T150	13		T62	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	6		T53	1		T141	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	13		T16	1		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T18	2		T20	17		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T129	12		T53	1		T27	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T62	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T275	2		T309	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T274	7		T283	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T62	1		T152	17		T43	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T146	19		T148	8		T227	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T26	1		T156	7		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T176	11		T225	17		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T17	8		T61	5		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T95	8		T158	13		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T253	10		T261	10		T183	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T251	18		T238	7		T259	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T46	2		T205	3		T96	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T98	11		T177	1		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T231	10		T154	6		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	11		T222	15		T149	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T61	14		T225	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T62	8		T153	11		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T53	6		T252	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	11		T19	1		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T18	14		T45	16		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T53	7		T27	1		T156	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11