Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19072

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3401

1

T9

1

T12

1

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16473

1

T2

20

T3

14

T4

20

auto[1]

6000

1

T5

7

T13

5

T15

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	126	1			T263	1		T258	23		T266	1
values[0]	16	1			T309	16		-	-		-	-
values[1]	742	1			T62	3		T152	32		T230	14
values[2]	567	1			T42	1		T232	2		T26	5
values[3]	623	1			T15	13		T17	9		T46	5
values[4]	500	1			T12	1		T264	1		T95	17
values[5]	826	1			T46	3		T144	1		T205	4
values[6]	702	1			T128	1		T150	4		T25	1
values[7]	683	1			T9	1		T13	5		T15	12
values[8]	840	1			T5	7		T14	24		T16	1
values[9]	3247	1			T18	16		T20	17		T38	2
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	654	1			T42	1		T152	32		T43	8
values[1]	556	1			T46	5		T144	1		T94	1
values[2]	705	1			T15	13		T17	9		T61	11
values[3]	544	1			T12	1		T46	3		T95	17
values[4]	815	1			T150	4		T144	1		T264	1
values[5]	671	1			T15	12		T128	1		T62	19
values[6]	3054	1			T9	1		T13	5		T16	1
values[7]	747	1			T5	7		T14	24		T19	4
values[8]	864	1			T129	3		T47	25		T53	8
values[9]	48	1			T202	1		T180	8		T307	21
minimum	13815	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	6		T167	1		T313	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T42	1		T152	18		T176	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	1		T144	1		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T225	18		T154	10		T166	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	9		T61	6		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	1		T205	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	3		T250	21		T255	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	1		T95	9		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T150	1		T144	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T94	1		T96	8		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T25	1		T231	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T128	1		T62	9		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T13	4		T18	16		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	1		T16	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	5		T19	3		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	12		T53	10		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T129	1		T47	13		T62	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T53	8		T167	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T180	2		T307	11		T314	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T202	1		T308	1		T206	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13539	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T230	1		T146	20		T131	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T43	2		T167	5		T196	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	14		T246	14		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T46	4		T232	1		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T225	19		T166	17		T131	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T61	5		T225	1		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	12		T158	8		T228	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T250	5		T255	10		T157	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T95	8		T167	11		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T150	3		T229	2		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T94	10		T98	11		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T15	11		T234	12		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T62	10		T153	11		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T13	1		T20	15		T39	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T40	2		T150	12		T149	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	2		T19	1		T129	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	12		T150	15		T142	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T129	2		T47	12		T62	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T167	7		T197	8		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T180	6		T307	10		T314	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T206	1		T306	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T230	13		T146	21		T131	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T263	1		T266	1		T180	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T258	12		T161	3		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T309	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T62	2		T43	6		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T152	18		T230	1		T146	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T232	1		T26	4		T149	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T42	1		T176	12		T225	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T17	9		T46	1		T61	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	1		T205	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T264	1		T132	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T95	9		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	3		T144	1		T205	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T94	1		T96	8		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T150	1		T25	1		T231	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T128	1		T145	12		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	4		T15	1		T225	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	1		T62	9		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	5		T19	3		T61	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	12		T16	1		T40	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T18	16		T20	2		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T53	18		T167	1		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T180	6		T316	10		T317	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T258	11		T161	8		T318	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T309	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T62	1		T43	2		T167	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T152	14		T230	13		T146	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T232	1		T26	1		T149	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T225	19		T166	17		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	4		T61	5		T225	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	12		T30	1		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	12		T196	9		T253	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T95	8		T167	11		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T250	5		T255	10		T157	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T94	10		T98	11		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T150	3		T229	2		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T149	11		T237	10		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T15	11		T225	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T62	10		T153	11		T149	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	2		T19	1		T61	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	12		T40	2		T150	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T20	15		T39	14		T129	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T167	7		T134	10		T197	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T43	6		T167	6		T313	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	1		T152	15		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	5		T144	1		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T225	20		T154	1		T166	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	1		T61	6		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	13		T205	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	1		T250	6		T255	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T95	9		T167	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T150	4		T144	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T94	11		T96	1		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	12		T25	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T128	1		T62	11		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T13	4		T18	2		T20	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T16	1		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	6		T19	3		T129	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	13		T53	1		T150	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T129	3		T47	13		T62	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	1		T167	8		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T180	7		T307	11		T314	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T202	1		T308	1		T206	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13642	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T230	14		T146	22		T131	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T43	2		T319	10		T275	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T152	17		T176	11		T148	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T26	1		T149	11		T239	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T225	17		T154	9		T166	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T17	8		T61	5		T252	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T158	13		T228	12		T259	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	2		T250	20		T255	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T95	8		T157	9		T259	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T205	3		T229	8		T248	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T96	7		T98	11		T222	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T231	10		T154	6		T233	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T62	8		T153	11		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T13	1		T18	14		T45	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	1		T175	10		T226	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T19	1		T53	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	11		T53	9		T142	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	12		T62	12		T143	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	7		T197	8		T254	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T180	1		T307	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T62	1		T233	15		T320	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T146	19		T227	19		T321	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T263	1		T266	1		T180	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T258	12		T161	9		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T309	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T62	2		T43	6		T167	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T152	15		T230	14		T146	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T232	2		T26	4		T149	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T42	1		T176	1		T225	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	1		T46	5		T61	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	13		T205	1		T30	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T264	1		T132	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T95	9		T167	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T46	1		T144	1		T205	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T94	11		T96	1		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T150	4		T25	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	1		T145	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	4		T15	12		T225	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	1		T62	11		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	6		T19	3		T61	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	13		T16	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T18	2		T20	17		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	2		T167	8		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T180	1		T270	9		T316	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T258	11		T161	2		T318	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T309	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T62	1		T43	2		T233	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T152	17		T146	19		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T26	1		T149	11		T239	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T176	11		T225	17		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T17	8		T61	5		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T158	13		T228	12		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T253	10		T261	10		T183	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T95	8		T157	9		T259	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	2		T205	3		T250	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T96	7		T98	11		T251	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T231	10		T154	6		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T145	11		T222	15		T149	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T225	7		T254	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T62	8		T153	11		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T19	1		T61	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	11		T40	1		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T18	14		T45	16		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	16		T197	8		T254	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11