Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5453	1			T1	20		T3	7		T4	20
testmodes[AdcCtrlTestmodeNormal]	4412	1			T3	7		T5	1		T6	8
testmodes[AdcCtrlTestmodeLowpower]	4543	1			T5	2		T8	14		T9	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2885	1			T1	19		T3	2		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1358	1			T3	5		T6	2		T10	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1105	1			T19	1		T40	1		T48	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1365	1			T3	5		T6	1		T10	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1619	1			T3	1		T6	6		T10	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1085	1			T13	1		T19	1		T40	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1089	1			T40	1		T41	1		T48	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1096	1			T5	1		T12	1		T19	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2108	1			T5	1		T8	13		T9	10