Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19451

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3305

1

T11

3

T14

3

T15

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16687

1

T1

20

T3

14

T4

20

auto[1]

6069

1

T12

3

T15

27

T17

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	87	1			T100	11		T237	9		T238	1
values[1]	731	1			T13	5		T19	5		T79	1
values[2]	754	1			T11	3		T40	5		T41	3
values[3]	606	1			T14	3		T15	27		T132	13
values[4]	3182	1			T18	2		T80	3		T46	8
values[5]	747	1			T20	10		T128	10		T38	12
values[6]	731	1			T16	1		T79	1		T137	13
values[7]	501	1			T13	6		T129	33		T213	11
values[8]	817	1			T12	3		T130	15		T30	4
values[9]	1090	1			T17	16		T130	14		T131	1
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	937	1			T13	5		T19	5		T40	5
values[1]	786	1			T11	3		T15	27		T41	3
values[2]	633	1			T14	3		T132	13		T138	5
values[3]	3174	1			T18	2		T80	3		T46	8
values[4]	726	1			T20	10		T79	1		T129	44
values[5]	763	1			T13	6		T16	1		T38	12
values[6]	591	1			T129	33		T178	8		T101	11
values[7]	707	1			T12	3		T130	15		T30	4
values[8]	770	1			T17	16		T130	14		T131	1
values[9]	158	1			T239	13		T240	23		T241	23
minimum	13511	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	3		T19	5		T128	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T40	5		T79	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T177	16		T134	10		T149	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	3		T15	15		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T132	11		T138	5		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T97	11		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1764	1			T18	2		T80	1		T46	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T131	1		T150	8		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T97	8		T141	11		T163	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	10		T79	1		T129	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	2		T16	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T38	3		T137	8		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T129	16		T178	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T213	9		T244	21		T163	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	2		T130	1		T43	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	3		T31	3		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T17	8		T130	1		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T130	1		T131	1		T42	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T245	1		T246	1		T247	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T239	1		T240	11		T241	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13413	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	2		T128	9		T134	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T100	10		T248	4		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T177	11		T134	9		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	12		T146	9		T97	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T132	2		T101	9		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	2		T142	12		T249	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T80	2		T136	16		T175	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T177	1		T146	14		T250	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T97	2		T141	10		T164	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T129	20		T149	11		T39	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	4		T243	8		T244	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	9		T137	5		T251	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T129	17		T178	7		T101	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T213	2		T244	19		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T130	14		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	1		T31	1		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T17	8		T130	8		T178	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T130	4		T100	16		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T245	1		T246	9		T187	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T239	12		T240	12		T241	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T237	9		T253	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T100	1		T238	1		T254	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	3		T19	5		T128	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T79	1		T96	1		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T176	7		T134	10		T149	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	3		T40	5		T41	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	11		T138	5		T177	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T15	15		T97	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1734	1			T18	2		T80	1		T46	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T150	8		T177	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T128	10		T193	13		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T20	10		T38	3		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	1		T244	11		T255	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T79	1		T137	8		T129	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	2		T129	16		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T213	9		T140	1		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	2		T130	1		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	3		T31	3		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T17	8		T130	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T130	1		T131	1		T42	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T253	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T100	10		T256	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	2		T128	9		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T257	2		T248	4		T258	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T134	9		T149	2		T259	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	9		T260	11		T257	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	2		T177	11		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	2		T15	12		T97	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T80	2		T136	16		T175	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T177	1		T146	14		T250	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T193	18		T97	2		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T38	9		T129	10		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T244	11		T255	11		T261	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	5		T129	10		T39	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	4		T129	17		T262	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T213	2		T251	13		T141	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T130	14		T178	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T30	1		T31	1		T222	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T17	8		T130	8		T178	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T130	4		T100	16		T142	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	3		T19	4		T128	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T40	4		T79	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T177	12		T134	10		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	2		T15	13		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	3		T138	1		T101	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	3		T97	1		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T18	2		T80	3		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T131	1		T150	1		T177	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T97	3		T141	11		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	1		T79	1		T129	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	5		T16	1		T243	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	10		T137	6		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T129	18		T178	8		T101	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T213	3		T244	21		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	2		T130	15		T43	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T30	3		T31	3		T222	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T17	9		T130	9		T178	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T130	5		T131	1		T42	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T245	2		T246	10		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T239	13		T240	13		T241	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13511	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	2		T19	1		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T40	1		T144	11		T263	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T177	15		T134	9		T149	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	1		T15	14		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T132	10		T138	4		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T97	10		T142	13		T249	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T46	7		T49	19		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T150	7		T250	7		T152	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T97	7		T141	10		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T20	9		T129	22		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	1		T244	10		T255	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T38	2		T137	7		T264	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T129	15		T152	18		T265	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T213	8		T244	19		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T43	1		T151	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	1		T31	1		T259	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T17	7		T138	10		T94	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T176	11		T266	4		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T247	8		T187	10		T267	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T240	10		T241	10		T268	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T237	1		T253	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T100	11		T238	1		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	3		T19	4		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T79	1		T96	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T176	1		T134	10		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	2		T40	4		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	3		T138	1		T177	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	3		T15	13		T97	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T18	2		T80	3		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T150	1		T177	2		T146	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T128	1		T193	19		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	1		T38	10		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	1		T244	12		T255	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T79	1		T137	6		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	5		T129	18		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T213	3		T140	1		T251	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	2		T130	15		T178	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T30	3		T31	3		T222	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T17	9		T130	9		T178	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T130	5		T131	1		T42	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T237	8		T253	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T254	2		T269	15		T256	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	2		T19	1		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T144	11		T263	8		T248	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T176	6		T134	9		T149	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T40	1		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	10		T138	4		T177	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	14		T97	9		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T46	7		T49	19		T174	43
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T150	7		T97	10		T250	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T128	9		T193	12		T97	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	9		T38	2		T129	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T244	10		T255	4		T261	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T137	7		T129	15		T39	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T13	1		T129	15		T270	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T213	8		T141	13		T259	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T43	1		T151	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	1		T31	1		T244	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T17	7		T138	10		T94	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T176	11		T266	4		T206	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19224

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3532

1

T13

5

T17

16

T130

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16449

1

T1

20

T3

14

T4

20

auto[1]

6307

1

T12

3

T13

5

T18

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T271	8		-	-		-	-
values[0]	1	1			T272	1		-	-		-	-
values[1]	688	1			T129	44		T138	5		T177	1
values[2]	715	1			T128	21		T129	33		T191	19
values[3]	462	1			T11	3		T19	5		T79	1
values[4]	668	1			T16	1		T177	2		T146	15
values[5]	3071	1			T12	3		T13	5		T17	16
values[6]	678	1			T40	5		T131	1		T150	21
values[7]	760	1			T79	1		T41	3		T131	1
values[8]	606	1			T20	10		T130	9		T131	1
values[9]	1589	1			T13	6		T14	3		T15	27
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T129	44		T177	1		T146	13
values[1]	637	1			T128	21		T129	33		T191	19
values[2]	459	1			T11	3		T19	5		T79	1
values[3]	3071	1			T13	5		T16	1		T18	2
values[4]	699	1			T12	3		T17	16		T40	5
values[5]	754	1			T79	1		T41	3		T131	1
values[6]	655	1			T130	9		T131	1		T176	12
values[7]	816	1			T15	27		T20	10		T128	10
values[8]	1066	1			T13	6		T14	3		T94	6
values[9]	253	1			T130	15		T137	13		T182	1
minimum	13515	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T129	16		T146	1		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T129	8		T177	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T128	12		T191	14		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T129	16		T31	3		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	3		T19	5		T79	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	3		T100	1		T149	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1708	1			T16	1		T18	2		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	3		T178	1		T213	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	2		T40	5		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	8		T130	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T79	1		T150	8		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T41	3		T131	1		T150	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T131	1		T176	12		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T130	1		T177	16		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	15		T20	10		T193	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T128	10		T131	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	2		T14	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T94	6		T149	11		T152	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T137	8		T182	1		T164	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T130	1		T32	2		T273	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T138	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	10		T146	12		T213	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T129	10		T222	6		T274	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T128	9		T191	5		T101	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T129	17		T31	1		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T132	2		T275	5		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T38	9		T100	10		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T80	2		T136	16		T175	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	2		T178	3		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T146	14		T276	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	8		T130	4		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	1		T250	9		T251	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T178	7		T100	12		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T44	1		T134	2		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T130	8		T177	11		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	12		T193	18		T97	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T146	9		T97	9		T100	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	4		T14	2		T260	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T149	11		T152	5		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T137	5		T164	17		T277	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T130	14		T32	2		T273	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3