Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19223

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3533

1

T13

5

T17

16

T130

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16437

1

T1

20

T3

14

T4

20

auto[1]

6319

1

T12

3

T13

5

T18

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	331	1			T149	31		T32	4		T242	1
values[0]	2	1			T357	1		T272	1		-	-
values[1]	648	1			T129	44		T138	5		T177	1
values[2]	741	1			T128	21		T129	33		T191	19
values[3]	474	1			T11	3		T19	5		T79	1
values[4]	640	1			T16	1		T132	13		T177	2
values[5]	3083	1			T12	3		T13	5		T17	16
values[6]	709	1			T40	5		T41	3		T131	1
values[7]	693	1			T79	1		T131	1		T176	19
values[8]	669	1			T20	10		T130	9		T128	10
values[9]	1256	1			T13	6		T14	3		T15	27
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	547	1			T129	44		T177	1		T213	10
values[1]	649	1			T128	21		T129	33		T191	19
values[2]	478	1			T11	3		T19	5		T79	1
values[3]	3127	1			T13	5		T16	1		T18	2
values[4]	681	1			T12	3		T17	16		T40	5
values[5]	709	1			T79	1		T41	3		T131	1
values[6]	738	1			T130	9		T131	1		T176	12
values[7]	714	1			T20	10		T128	10		T131	1
values[8]	1196	1			T13	6		T14	3		T15	27
values[9]	153	1			T130	15		T182	1		T32	4
minimum	13764	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T129	16		T213	1		T205	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T129	8		T177	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T128	12		T191	14		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	16		T31	3		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	3		T19	5		T79	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T38	3		T100	1		T149	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1734	1			T16	1		T18	2		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	3		T178	1		T213	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	2		T40	5		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	8		T130	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T79	1		T150	8		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	3		T131	1		T150	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	1		T176	12		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T130	1		T177	16		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	10		T193	13		T97	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T128	10		T131	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T13	2		T14	1		T15	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T94	6		T149	11		T152	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T182	1		T277	2		T185	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T130	1		T32	2		T273	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13470	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T138	5		T274	11		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T129	10		T213	9		T278	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T129	10		T222	6		T262	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T128	9		T191	5		T101	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T129	17		T31	1		T196	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T132	2		T275	5		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T38	9		T100	10		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1105	1			T80	2		T136	16		T175	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	2		T178	3		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T276	10		T301	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	8		T130	4		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	1		T250	9		T251	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T178	7		T100	12		T303	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T101	10		T44	1		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	8		T177	11		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T193	18		T97	2		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T146	9		T97	9		T100	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	4		T14	2		T15	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T149	11		T152	5		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T277	1		T185	10		T358	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T130	14		T32	2		T273	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T274	10		T306	9		T184	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T149	7		T242	1		T248	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T149	11		T32	2		T163	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T357	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T129	16		T146	1		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T129	8		T138	5		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T128	12		T191	14		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T129	16		T135	1		T203	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	3		T19	5		T79	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	3		T149	5		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T16	1		T132	11		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T100	1		T275	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T12	2		T18	2		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	3		T17	8		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	5		T150	8		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	3		T131	1		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T79	1		T131	1		T176	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T176	7		T177	16		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T20	10		T97	8		T134	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T130	1		T128	10		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T13	2		T14	1		T15	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T130	1		T94	6		T100	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T149	2		T248	4		T164	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T149	11		T32	2		T323	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	10		T146	12		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T129	10		T222	6		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T128	9		T191	5		T101	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	17		T196	9		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T275	5		T143	11		T257	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T38	9		T149	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T132	2		T177	1		T146	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T100	10		T275	8		T278	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T12	1		T80	2		T136	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	2		T17	8		T130	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	1		T250	9		T251	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T178	7		T43	1		T100	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T101	10		T44	1		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T177	11		T276	6		T244	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T97	2		T134	2		T280	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T130	8		T146	9		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	4		T14	2		T15	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T130	14		T100	16		T279	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	11		T213	10		T205	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T129	11		T177	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T128	10		T191	6		T101	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	18		T31	3		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	2		T19	4		T79	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	10		T100	11		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T16	1		T18	2		T80	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	3		T178	4		T213	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T40	4		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	9		T130	5		T54	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T79	1		T150	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T41	2		T131	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	1		T176	1		T101	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T130	9		T177	12		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	1		T193	19		T97	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T128	1		T131	1		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T13	5		T14	3		T15	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T94	1		T149	12		T152	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T182	1		T277	2		T185	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T130	15		T32	4		T273	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13585	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T138	1		T274	11		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T129	15		T278	16		T209	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T129	7		T282	15		T344	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T128	11		T191	13		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T129	15		T31	1		T203	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T19	1		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T38	2		T149	4		T281	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T46	7		T49	19		T174	43
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	2		T213	8		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T40	1		T266	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T17	7		T43	1		T97	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T150	7		T30	1		T250	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T41	1		T150	12		T176	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T176	11		T44	1		T134	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T177	15		T279	15		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T20	9		T193	12		T97	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T128	9		T97	9		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T13	1		T15	14		T137	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T94	5		T149	10		T152	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T277	1		T185	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T273	19		T282	5		T283	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T297	15		T298	8		T359	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T138	4		T274	10		T306	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T149	3		T242	1		T248	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T149	12		T32	4		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T357	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T129	11		T146	13		T213	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T129	11		T138	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T128	10		T191	6		T101	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T129	18		T135	1		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	2		T19	4		T79	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	10		T149	3		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	1		T132	3		T177	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T100	11		T275	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T12	2		T18	2		T80	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	3		T17	9		T130	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	4		T150	1		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	2		T131	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T79	1		T131	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T176	1		T177	12		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T20	1		T97	3		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T130	9		T128	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T13	5		T14	3		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T130	15		T94	1		T100	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T149	6		T248	2		T164	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T149	10		T163	11		T154	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	15		T278	16		T209	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T129	7		T138	4		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T128	11		T191	13		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T129	15		T203	18		T196	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	1		T19	1		T151	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T38	2		T149	4		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T132	10		T141	13		T242	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T144	11		T278	8		T323	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T12	1		T46	7		T49	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	2		T17	7		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	1		T150	7		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	1		T150	12		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T176	11		T44	1		T264	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T176	6		T177	15		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	9		T97	7		T134	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T128	9		T97	9		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T13	1		T15	14		T137	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T94	5		T279	8		T152	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3