Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19458

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3298

1

T11

3

T14

3

T15

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16687

1

T1

20

T3

14

T4

20

auto[1]

6069

1

T12

3

T15

27

T17

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T100	17		T263	11		T287	1
values[0]	40	1			T100	11		T254	3		T256	26
values[1]	741	1			T13	5		T19	5		T79	1
values[2]	782	1			T11	3		T40	5		T41	3
values[3]	708	1			T14	3		T15	27		T132	13
values[4]	3124	1			T18	2		T80	3		T46	8
values[5]	727	1			T20	10		T128	10		T38	12
values[6]	752	1			T13	6		T16	1		T79	1
values[7]	507	1			T129	33		T178	8		T213	11
values[8]	793	1			T12	3		T130	15		T30	4
values[9]	787	1			T17	16		T130	14		T131	1
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T13	5		T19	5		T79	1
values[1]	719	1			T15	27		T40	5		T41	3
values[2]	657	1			T11	3		T14	3		T132	13
values[3]	3233	1			T18	2		T20	10		T80	3
values[4]	624	1			T79	1		T129	44		T97	10
values[5]	764	1			T13	6		T16	1		T38	12
values[6]	620	1			T129	33		T101	11		T213	11
values[7]	756	1			T12	3		T130	15		T30	4
values[8]	786	1			T17	16		T130	14		T131	1
values[9]	109	1			T239	13		T241	23		T268	16
minimum	13793	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	3		T19	5		T128	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T79	1		T96	1		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T177	16		T134	10		T149	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	15		T40	5		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	11		T138	5		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	3		T14	1		T97	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1793	1			T18	2		T80	1		T46	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	10		T131	1		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T97	8		T243	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T79	1		T129	24		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	2		T16	1		T244	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	3		T137	8		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T129	16		T101	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T213	9		T244	11		T163	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	2		T130	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	3		T31	3		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T17	8		T130	1		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	1		T131	1		T42	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T245	1		T247	9		T187	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T239	1		T241	11		T268	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13481	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T100	1		T348	17		T238	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	2		T128	9		T274	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T257	2		T248	4		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T177	11		T134	9		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	12		T146	9		T260	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T132	2		T54	4		T101	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	2		T97	9		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T80	2		T136	16		T175	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T177	1		T146	14		T250	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T97	2		T243	8		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T129	20		T149	11		T222	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	4		T244	11		T255	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	9		T137	5		T39	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	17		T101	10		T152	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T213	2		T244	7		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T130	14		T178	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	1		T31	1		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T17	8		T130	8		T178	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T130	4		T100	16		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T245	1		T187	11		T267	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T239	12		T241	12		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T100	10		T185	10		T305	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T263	11		T287	1		T261	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T100	1		T165	1		T357	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T100	1		T254	3		T256	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	3		T19	5		T128	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T79	1		T96	1		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T134	10		T149	7		T259	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	3		T40	5		T41	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T132	11		T138	5		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	1		T15	15		T97	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1743	1			T18	2		T80	1		T46	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T150	8		T177	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T128	10		T133	1		T97	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	10		T38	3		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	2		T16	1		T244	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T79	1		T137	8		T129	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T129	16		T178	1		T152	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T213	9		T264	6		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	2		T130	1		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T30	3		T31	3		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T17	8		T130	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T130	1		T131	1		T42	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T261	10		T33	1		T155	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T100	16		T165	8		T268	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T100	10		T256	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T128	9		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T248	4		T258	14		T157	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T134	9		T149	2		T259	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T146	9		T260	11		T257	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T132	2		T54	4		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	2		T15	12		T97	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T80	2		T136	16		T175	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T177	1		T146	14		T250	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T97	2		T243	8		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T38	9		T129	10		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	4		T244	11		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T137	5		T129	10		T39	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T129	17		T178	7		T152	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T213	2		T251	13		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T130	14		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	1		T31	1		T222	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T17	8		T130	8		T178	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T130	4		T142	1		T239	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	3		T19	4		T128	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T79	1		T96	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T177	12		T134	10		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	13		T40	4		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T132	3		T138	1		T54	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	2		T14	3		T97	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T18	2		T80	3		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T20	1		T131	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T97	3		T243	9		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T79	1		T129	22		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	5		T16	1		T244	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	10		T137	6		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T129	18		T101	11		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T213	3		T244	8		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	2		T130	15		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	3		T31	3		T222	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T17	9		T130	9		T178	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	5		T131	1		T42	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T245	2		T247	1		T187	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T239	13		T241	13		T268	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13570	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T100	11		T348	1		T238	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T19	1		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	11		T263	8		T248	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T177	15		T134	9		T149	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	14		T40	1		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	10		T138	4		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T97	19		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T46	7		T49	19		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T20	9		T150	7		T250	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T97	7		T141	10		T164	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T129	22		T149	10		T222	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	1		T244	10		T255	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	2		T137	7		T39	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T129	15		T152	18		T265	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T213	8		T244	10		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T43	1		T151	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	1		T31	1		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	7		T138	10		T94	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T176	11		T266	4		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T247	8		T187	10		T267	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T241	10		T268	13		T341	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T134	7		T324	12		T277	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T348	16		T283	9		T185	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T263	1		T287	1		T261	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T100	17		T165	9		T357	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T100	11		T254	1		T256	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	3		T19	4		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T79	1		T96	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T134	10		T149	3		T259	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	2		T40	4		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	3		T138	1		T54	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	3		T15	13		T97	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T18	2		T80	3		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T150	1		T177	2		T146	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T128	1		T133	1		T97	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	1		T38	10		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	5		T16	1		T244	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T79	1		T137	6		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T129	18		T178	8		T152	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T213	3		T264	1		T251	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	2		T130	15		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	3		T31	3		T222	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T17	9		T130	9		T178	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T130	5		T131	1		T42	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T263	10		T261	11		T265	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T156	6		T268	13		T360	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T254	2		T256	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	2		T19	1		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T144	11		T263	8		T248	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	9		T149	6		T259	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T40	1		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T132	10		T138	4		T177	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	14		T97	19		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T46	7		T49	19		T174	43
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T150	7		T250	7		T152	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T128	9		T97	7		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	9		T38	2		T129	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T244	10		T255	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T137	7		T129	15		T39	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T129	15		T152	18		T282	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T213	8		T264	5		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	1		T43	1		T151	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T30	1		T31	1		T244	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	7		T138	10		T94	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T176	11		T266	4		T206	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3