Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19493

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3263

1

T12

3

T20

10

T40

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16463

1

T1

20

T3

14

T4

20

auto[1]

6293

1

T13

5

T14

3

T18

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T11	3		T177	27		T146	10
values[0]	46	1			T250	17		T320	3		T339	24
values[1]	830	1			T193	31		T54	5		T133	1
values[2]	614	1			T131	1		T191	19		T176	12
values[3]	886	1			T138	16		T146	13		T100	11
values[4]	581	1			T16	1		T178	4		T96	1
values[5]	692	1			T12	3		T14	3		T19	5
values[6]	733	1			T128	21		T131	1		T42	2
values[7]	519	1			T38	12		T131	1		T129	44
values[8]	3121	1			T13	11		T15	27		T18	2
values[9]	987	1			T17	16		T20	10		T79	1
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	728	1			T131	1		T54	5		T133	1
values[1]	721	1			T191	19		T176	12		T97	19
values[2]	843	1			T178	4		T138	16		T146	13
values[3]	590	1			T12	3		T16	1		T41	3
values[4]	727	1			T14	3		T19	5		T40	5
values[5]	647	1			T128	21		T38	12		T131	1
values[6]	2993	1			T13	5		T18	2		T80	3
values[7]	708	1			T13	6		T15	27		T130	20
values[8]	849	1			T11	3		T17	16		T20	10
values[9]	168	1			T150	8		T146	10		T43	4
minimum	13782	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T131	1		T286	1		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T54	1		T133	1		T39	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T191	14		T97	10		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T176	12		T101	1		T151	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T178	1		T138	5		T279	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T138	11		T146	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T96	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	2		T41	3		T150	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	1		T19	5		T79	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	5		T44	4		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	12		T131	1		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	3		T42	2		T129	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T13	3		T18	2		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T178	1		T97	11		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	2		T15	15		T130	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T128	10		T177	1		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T11	3		T17	8		T79	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T20	10		T130	1		T129	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T146	1		T43	3		T143	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T150	8		T298	4		T170	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13473	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T193	13		T100	1		T260	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T31	1		T274	4		T278	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	4		T39	12		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T191	5		T97	9		T100	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T101	10		T320	4		T361	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T178	3		T279	14		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T146	12		T222	11		T209	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T141	12		T259	5		T362	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T177	1		T97	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	2		T146	14		T152	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	1		T239	12		T255	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T128	9		T132	2		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	9		T129	10		T274	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T13	2		T80	2		T136	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T178	7		T100	12		T301	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T15	12		T130	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T101	9		T149	11		T239	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T17	8		T137	5		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T130	8		T129	17		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T146	9		T43	1		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T298	6		T170	21		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T193	18		T100	16		T260	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T11	3		T177	16		T146	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T264	11		T257	1		T306	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T250	8		T320	1		T339	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T363	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T94	6		T213	9		T274	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T193	13		T54	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T131	1		T191	14		T97	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T176	12		T101	1		T151	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T138	5		T100	1		T279	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T138	11		T146	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	1		T178	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T152	19		T276	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	1		T19	5		T79	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	2		T40	5		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T128	12		T131	1		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T42	2		T151	4		T274	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T131	1		T129	8		T149	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	3		T129	16		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1774	1			T13	5		T15	15		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T149	11		T292	1		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T17	8		T79	1		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T20	10		T130	1		T128	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T177	11		T146	9		T143	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T257	9		T306	9		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T250	9		T320	2		T339	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T213	2		T274	4		T278	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T193	18		T54	4		T100	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T191	5		T97	9		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T101	10		T213	9		T320	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T100	10		T279	2		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T146	12		T222	11		T209	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T178	3		T279	12		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T152	20		T276	10		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	2		T146	14		T275	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T177	1		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T128	9		T132	2		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T274	10		T276	6		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T129	10		T149	2		T242	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	9		T129	10		T178	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T13	6		T15	12		T80	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T149	11		T301	2		T360	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T17	8		T137	5		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T130	8		T129	17		T30	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T131	1		T286	1		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T54	5		T133	1		T39	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T191	6		T97	10		T100	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T176	1		T101	11		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T178	4		T138	1		T279	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T138	1		T146	13		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	1		T96	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	2		T41	2		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T14	3		T19	4		T79	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	4		T44	4		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T128	10		T131	1		T132	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	10		T42	2		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T13	3		T18	2		T80	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T178	8		T97	1		T100	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	5		T15	13		T130	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T128	1		T177	1		T101	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T11	2		T17	9		T79	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	1		T130	9		T129	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T146	10		T43	3		T143	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T150	1		T298	7		T170	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13545	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T193	19		T100	17		T260	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	1		T274	2		T278	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	11		T274	2		T259	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T191	13		T97	9		T259	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T176	11		T151	18		T263	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T138	4		T279	23		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T138	10		T222	10		T265	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T141	13		T259	6		T284	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T41	1		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	1		T152	15		T264	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T40	1		T44	1		T255	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T128	11		T132	10		T176	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	2		T129	15		T151	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T13	2		T46	7		T49	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T97	10		T323	2		T354	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T15	14		T134	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T128	9		T149	10		T266	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T17	7		T137	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T20	9		T129	15		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T43	1		T143	9		T90	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T150	7		T298	3		T170	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T94	5		T213	8		T250	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T193	12		T242	10		T346	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	2		T177	12		T146	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T264	1		T257	10		T306	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T250	10		T320	3		T339	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T363	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T94	1		T213	3		T274	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T193	19		T54	5		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T131	1		T191	6		T97	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T176	1		T101	11		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T138	1		T100	11		T279	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T138	1		T146	13		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	1		T178	4		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T152	21		T276	11		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	3		T19	4		T79	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	2		T40	4		T41	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T128	10		T131	1		T132	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	2		T151	1		T274	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T131	1		T129	11		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	10		T129	11		T178	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T13	8		T15	13		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T149	12		T292	1		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T17	9		T79	1		T137	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T20	1		T130	9		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T11	1		T177	15		T143	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T264	10		T306	9		T364	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T250	7		T339	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T94	5		T213	8		T274	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T193	12		T39	11		T274	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T191	13		T97	9		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T176	11		T151	18		T291	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T138	4		T279	8		T196	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	10		T222	10		T263	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T279	15		T141	13		T285	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T152	18		T196	4		T273	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T19	1		T264	5		T259	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T40	1		T41	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T128	11		T132	10		T176	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	3		T274	10		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T129	7		T149	4		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	2		T129	15		T97	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T13	3		T15	14		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	10		T266	4		T281	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	7		T137	7		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	9		T128	9		T150	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3