Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19359

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3397

1

T13

11

T16

1

T19

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16229

1

T1

20

T3

14

T4

20

auto[1]

6527

1

T5

1

T11

3

T12

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	621	1			T5	1		T12	2		T19	8
values[0]	94	1			T137	13		T213	10		T333	31
values[1]	656	1			T11	3		T17	16		T131	1
values[2]	2977	1			T14	3		T16	1		T18	2
values[3]	600	1			T131	2		T193	31		T97	11
values[4]	761	1			T40	5		T79	1		T129	33
values[5]	703	1			T41	3		T128	10		T129	44
values[6]	711	1			T20	10		T178	8		T97	10
values[7]	642	1			T150	8		T44	5		T134	19
values[8]	882	1			T13	5		T15	27		T79	1
values[9]	887	1			T12	3		T13	6		T128	21
minimum	13222	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	579	1			T11	3		T19	5		T131	1
values[1]	3129	1			T14	3		T16	1		T18	2
values[2]	494	1			T40	5		T79	1		T131	1
values[3]	719	1			T128	10		T129	33		T191	19
values[4]	653	1			T41	3		T129	18		T132	13
values[5]	769	1			T20	10		T129	26		T178	8
values[6]	734	1			T15	27		T150	8		T54	5
values[7]	861	1			T13	5		T79	1		T177	27
values[8]	872	1			T12	3		T13	6		T130	14
values[9]	133	1			T182	1		T142	26		T163	12
minimum	13813	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T42	2		T176	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T19	5		T131	1		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T14	1		T18	2		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	1		T97	11		T151	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T79	1		T131	1		T193	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T40	5		T133	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T128	10		T191	14		T138	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T129	16		T94	6		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T132	11		T100	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	3		T129	8		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T279	16		T275	1		T242	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	10		T129	16		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T15	15		T54	1		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T150	8		T177	1		T44	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T79	1		T100	1		T149	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	3		T177	16		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T12	2		T38	3		T150	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	2		T130	2		T128	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T182	1		T288	1		T365	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T142	14		T163	12		T270	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13514	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T146	1		T141	14		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T244	23		T241	4		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	1		T43	1		T152	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T14	2		T80	2		T136	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T213	2		T259	12		T278	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T193	18		T134	2		T323	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T101	10		T33	1		T321	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T191	5		T177	1		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T129	17		T31	1		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	2		T100	10		T152	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T129	10		T279	2		T255	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T279	12		T275	8		T242	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T129	10		T178	7		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	12		T54	4		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T44	1		T39	12		T294	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T100	16		T149	2		T222	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	2		T177	11		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	1		T38	9		T146	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	4		T130	12		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T288	2		T365	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T142	12		T155	12		T298	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	2		T16	1		T17	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T146	9		T141	12		T302	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T5	1		T12	2		T19	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T130	2		T138	5		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T137	8		T213	1		T333	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T366	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	3		T17	8		T176	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T131	1		T30	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T14	1		T18	2		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	1		T19	5		T213	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T131	2		T193	13		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T97	11		T101	1		T151	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T79	1		T191	14		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	5		T129	16		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T128	10		T132	11		T152	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T41	3		T129	24		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T100	1		T279	16		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T20	10		T178	1		T97	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T134	10		T149	7		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T150	8		T44	4		T287	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	15		T79	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	3		T177	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T12	2		T38	3		T176	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	2		T128	12		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13124	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T146	14		T274	3		T288	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T130	12		T260	11		T142	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T137	5		T213	9		T333	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T366	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	8		T244	23		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	1		T146	9		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T14	2		T80	2		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T213	2		T152	20		T259	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T193	18		T134	2		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T101	10		T33	1		T297	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T191	5		T177	1		T274	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T129	17		T31	1		T244	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T132	2		T152	5		T251	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T129	20		T279	2		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T100	10		T279	12		T275	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T178	7		T97	2		T100	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T134	9		T149	2		T250	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T44	1		T255	1		T294	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	12		T54	4		T100	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	2		T146	12		T39	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T38	9		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	4		T128	9		T178	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	2		T42	2		T176	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T19	4		T131	1		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T14	3		T18	2		T80	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	1		T97	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T79	1		T131	1		T193	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	4		T133	1		T101	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T128	1		T191	6		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T129	18		T94	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T132	3		T100	11		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	2		T129	11		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T279	13		T275	9		T242	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T20	1		T129	11		T178	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	13		T54	5		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T150	1		T177	1		T44	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T79	1		T100	17		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	3		T177	12		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T12	2		T38	10		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	5		T130	14		T128	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T182	1		T288	3		T365	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T142	13		T163	1		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13614	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T146	10		T141	13		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	1		T176	6		T244	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T19	1		T30	1		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T46	7		T49	19		T174	43
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T97	10		T151	18		T213	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T193	12		T134	7		T323	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T40	1		T154	11		T285	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	9		T191	13		T138	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T129	15		T94	5		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T132	10		T152	15		T259	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	1		T129	7		T279	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T279	15		T242	10		T280	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T20	9		T129	15		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	14		T134	9		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T150	7		T44	1		T39	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T149	4		T222	10		T274	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	2		T177	15		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	1		T38	2		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T128	11		T138	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T365	1		T254	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T142	13		T163	11		T270	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T17	7		T137	7		T333	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T141	13		T144	11		T90	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T5	1		T12	2		T19	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T130	14		T138	1		T260	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	6		T213	10		T333	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T366	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	2		T17	9		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T131	1		T30	3		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T14	3		T18	2		T80	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	1		T19	4		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T131	2		T193	19		T134	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T97	1		T101	11		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T79	1		T191	6		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T40	4		T129	18		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T128	1		T132	3		T152	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T41	2		T129	22		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T100	11		T279	13		T275	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T20	1		T178	8		T97	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	10		T149	3		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T150	1		T44	4		T287	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	13		T79	1		T54	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	3		T177	1		T146	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T12	2		T38	10		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	5		T128	10		T178	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13222	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T150	12		T274	2		T261	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T138	4		T142	13		T298	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T137	7		T333	14		T323	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T366	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	1		T17	7		T176	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T30	1		T43	1		T141	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T46	7		T49	19		T174	43
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	1		T213	8		T152	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T193	12		T134	7		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T97	10		T151	18		T297	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T191	13		T138	10		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	1		T129	15		T94	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T128	9		T132	10		T152	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T41	1		T129	22		T279	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T279	15		T242	10		T196	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	9		T97	7		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T134	9		T149	6		T250	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T150	7		T44	1		T294	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	14		T149	4		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	2		T39	21		T151	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T38	2		T176	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	1		T128	11		T177	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3