Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T271	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	16		T146	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T129	8		T138	5		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T128	12		T191	14		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T129	16		T135	1		T203	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T11	3		T19	5		T79	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	3		T149	5		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	1		T177	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T100	1		T275	1		T144	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T12	2		T18	2		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	3		T17	8		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	5		T150	8		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T131	1		T150	13		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T79	1		T131	1		T176	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T41	3		T176	7		T177	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T20	10		T97	8		T134	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T130	1		T131	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T13	2		T14	1		T15	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	486	1			T130	1		T128	10		T94	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T129	10		T146	12		T101	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T129	10		T222	6		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T128	9		T191	5		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T129	17		T196	9		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T132	2		T275	5		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T38	9		T149	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T177	1		T146	14		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T100	10		T275	8		T278	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T12	1		T80	2		T136	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	2		T17	8		T130	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	1		T250	9		T251	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T178	7		T43	1		T100	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T101	10		T44	1		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T177	11		T279	12		T276	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T97	2		T134	2		T280	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T130	8		T146	9		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T13	4		T14	2		T15	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T130	14		T100	16		T149	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T129	11		T146	13		T213	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T129	11		T177	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T128	10		T191	6		T101	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T129	18		T31	3		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	2		T19	4		T79	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	10		T100	11		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T16	1		T18	2		T80	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	3		T178	4		T213	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	2		T40	4		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	9		T130	5		T54	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T79	1		T150	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	2		T131	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T131	1		T176	1		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T130	9		T177	12		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	13		T20	1		T193	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T128	1		T131	1		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T13	5		T14	3		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T94	1		T149	12		T152	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T137	6		T182	1		T164	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T130	15		T32	4		T273	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T138	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T129	15		T278	16		T209	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T129	7		T274	10		T196	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T128	11		T191	13		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T129	15		T31	1		T203	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	1		T19	1		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T38	2		T149	4		T281	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T46	7		T49	19		T174	43
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	2		T213	8		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T40	1		T266	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T17	7		T43	1		T97	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	7		T30	1		T250	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T41	1		T150	12		T176	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T176	11		T44	1		T134	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T177	15		T279	15		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	14		T20	9		T193	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T128	9		T97	9		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	1		T149	6		T151	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T94	5		T149	10		T152	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	7		T164	18		T277	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T273	19		T282	5		T283	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T138	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T129	11		T146	13		T101	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T129	11		T138	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T128	10		T191	6		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T129	18		T135	1		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	2		T19	4		T79	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	10		T149	3		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T16	1		T177	2		T146	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T100	11		T275	9		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T12	2		T18	2		T80	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	3		T17	9		T130	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	4		T150	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	1		T150	1		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T79	1		T131	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T41	2		T176	1		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T20	1		T97	3		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T130	9		T131	1		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	452	1			T13	5		T14	3		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T130	15		T128	1		T94	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T271	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	15		T278	16		T209	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	7		T138	4		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T128	11		T191	13		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T129	15		T203	18		T196	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T11	1		T19	1		T132	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T38	2		T149	4		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T141	13		T242	11		T284	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T144	11		T278	8		T285	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T12	1		T46	7		T49	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	2		T17	7		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T40	1		T150	7		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T150	12		T138	10		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T176	11		T44	1		T264	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T41	1		T176	6		T177	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	9		T97	7		T134	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T97	9		T39	10		T259	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T13	1		T15	14		T137	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T128	9		T94	5		T149	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3