Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19178

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3578

1

T12

3

T13

5

T14

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16353

1

T1

20

T3

14

T4

20

auto[1]

6403

1

T5

1

T12

2

T13

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	289	1			T5	1		T12	2		T19	8
values[0]	163	1			T11	3		T137	13		T213	10
values[1]	534	1			T17	16		T131	1		T176	7
values[2]	2985	1			T16	1		T18	2		T19	5
values[3]	628	1			T14	3		T193	31		T133	1
values[4]	796	1			T40	5		T79	1		T129	33
values[5]	657	1			T41	3		T128	10		T129	44
values[6]	702	1			T20	10		T132	13		T178	8
values[7]	688	1			T150	8		T134	19		T149	9
values[8]	847	1			T13	5		T15	27		T79	1
values[9]	1245	1			T12	3		T13	6		T130	14
minimum	13222	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	892	1			T11	3		T17	16		T19	5
values[1]	3090	1			T14	3		T16	1		T18	2
values[2]	517	1			T40	5		T79	1		T131	1
values[3]	734	1			T128	10		T129	33		T191	19
values[4]	678	1			T41	3		T129	18		T132	13
values[5]	756	1			T20	10		T129	26		T178	8
values[6]	734	1			T15	27		T150	8		T54	5
values[7]	777	1			T13	5		T79	1		T177	27
values[8]	869	1			T12	3		T13	6		T130	14
values[9]	198	1			T182	1		T142	26		T163	12
minimum	13511	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	3		T17	8		T42	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	5		T131	1		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T18	2		T80	1		T46	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	1		T16	1		T286	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T193	13		T133	2		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	5		T79	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T128	10		T191	14		T138	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T129	16		T244	11		T257	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	3		T132	11		T152	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T129	8		T94	6		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T20	10		T129	16		T97	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T178	1		T100	1		T279	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	15		T54	1		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T150	8		T177	1		T44	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T177	16		T149	5		T287	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	3		T79	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T13	2		T38	3		T150	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	2		T130	2		T128	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T182	1		T288	1		T196	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T142	14		T163	12		T270	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13413	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T17	8		T137	5		T146	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	1		T43	1		T152	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T80	2		T136	16		T130	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	2		T213	2		T259	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T193	18		T101	10		T134	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T33	1		T262	1		T285	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T191	5		T177	1		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T129	17		T244	7		T257	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T132	2		T152	5		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T129	10		T100	10		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T129	10		T97	2		T275	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T178	7		T100	12		T279	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	12		T54	4		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T44	1		T39	12		T239	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T177	11		T149	2		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	2		T146	12		T100	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	4		T38	9		T146	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T130	12		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T288	2		T196	9		T289	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T142	12		T290	9		T155	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	1		T12	2		T19	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	3		T137	8		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T291	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	8		T176	7		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T131	1		T30	3		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T18	2		T80	1		T46	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	1		T19	5		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T193	13		T133	1		T97	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	1		T151	19		T292	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T191	14		T133	1		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T40	5		T79	1		T129	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T41	3		T128	10		T129	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T129	8		T94	6		T293	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	10		T132	11		T97	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T178	1		T96	1		T100	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T134	10		T149	7		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T150	8		T287	1		T294	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	15		T54	1		T177	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	3		T79	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	376	1			T13	2		T38	3		T150	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T12	2		T130	2		T128	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13124	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T137	5		T213	9		T244	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	8		T146	9		T141	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T30	1		T43	1		T276	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T80	2		T136	16		T130	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T213	2		T152	20		T259	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T193	18		T101	10		T134	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	2		T33	1		T241	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T191	5		T177	1		T274	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T129	17		T31	1		T279	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T129	10		T152	5		T255	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T129	10		T251	13		T259	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T132	2		T97	2		T275	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T178	7		T100	22		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	9		T149	2		T242	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T294	12		T207	4		T295	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	12		T54	4		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	2		T146	12		T100	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	4		T38	9		T146	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	1		T130	12		T128	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T11	2		T17	9		T42	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T19	4		T131	1		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T18	2		T80	3		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	3		T16	1		T286	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T193	19		T133	2		T101	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T40	4		T79	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T128	1		T191	6		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T129	18		T244	8		T257	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T41	2		T132	3		T152	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T129	11		T94	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	1		T129	11		T97	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T178	8		T100	13		T279	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	13		T54	5		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T150	1		T177	1		T44	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T177	12		T149	3		T287	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	3		T79	1		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	5		T38	10		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	2		T130	14		T128	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T182	1		T288	3		T196	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T142	13		T163	1		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13511	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T17	7		T137	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	1		T30	1		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T46	7		T49	19		T174	43
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	18		T213	8		T259	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T193	12		T134	7		T296	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T40	1		T154	11		T285	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T128	9		T191	13		T138	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	15		T244	10		T164	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	1		T132	10		T152	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T129	7		T94	5		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	9		T129	15		T97	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T279	15		T249	5		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	14		T134	9		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	7		T44	1		T39	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T177	15		T149	4		T261	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	2		T39	10		T151	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	1		T38	2		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T128	11		T138	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T196	11		T254	13		T256	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T142	13		T163	11		T270	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	1		T12	2		T19	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T11	2		T137	6		T213	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T291	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T17	9		T176	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	1		T30	3		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T18	2		T80	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	1		T19	4		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T193	19		T133	1		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	3		T151	1		T292	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T191	6		T133	1		T177	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T40	4		T79	1		T129	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T41	2		T128	1		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T129	11		T94	1		T293	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	1		T132	3		T97	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T178	8		T96	1		T100	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T134	10		T149	3		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	1		T287	1		T294	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T15	13		T54	5		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	3		T79	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T13	5		T38	10		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	2		T130	14		T128	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13222	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T11	1		T137	7		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T291	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T17	7		T176	6		T141	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T30	1		T43	1		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T46	7		T49	19		T174	43
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T19	1		T213	8		T152	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T193	12		T97	10		T134	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	18		T241	10		T297	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T191	13		T274	2		T278	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	1		T129	15		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	1		T128	9		T129	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T129	7		T94	5		T259	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T20	9		T132	10		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T149	10		T279	15		T249	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T134	9		T149	6		T264	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T150	7		T294	10		T265	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	14		T177	15		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	2		T44	1		T39	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T13	1		T38	2		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	1		T128	11		T138	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3