Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16909

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5847

1

T11

3

T12

3

T13

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16659

1

T1

20

T3

14

T4

20

auto[1]

6097

1

T12

3

T13

6

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	270	1			T19	5		T191	19		T146	15
values[1]	902	1			T11	3		T13	6		T41	3
values[2]	659	1			T146	13		T43	4		T101	11
values[3]	606	1			T12	3		T16	1		T20	10
values[4]	716	1			T79	1		T130	5		T38	12
values[5]	534	1			T13	5		T40	5		T131	1
values[6]	685	1			T130	9		T132	13		T138	5
values[7]	552	1			T128	10		T150	8		T193	31
values[8]	752	1			T14	3		T130	15		T42	2
values[9]	3570	1			T15	27		T17	16		T18	2
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	849	1			T11	3		T13	6		T129	33
values[1]	3034	1			T16	1		T18	2		T80	3
values[2]	665	1			T12	3		T20	10		T79	1
values[3]	673	1			T40	5		T130	5		T38	12
values[4]	588	1			T13	5		T131	1		T177	1
values[5]	621	1			T130	9		T150	8		T132	13
values[6]	681	1			T128	10		T42	2		T129	18
values[7]	658	1			T14	3		T130	15		T176	19
values[8]	1028	1			T15	27		T17	16		T19	5
values[9]	208	1			T191	19		T146	15		T97	29
minimum	13751	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T129	16		T177	16		T43	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	3		T13	2		T222	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	1		T149	16		T151	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1678	1			T18	2		T80	1		T46	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T20	10		T79	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	2		T129	16		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T130	1		T38	3		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	5		T146	1		T39	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T177	1		T260	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	3		T131	1		T94	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	11		T138	5		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T130	1		T150	8		T193	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	8		T97	11		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T128	10		T42	2		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T130	1		T176	19		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T182	1		T259	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T19	5		T150	13		T138	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T15	15		T17	8		T79	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T191	14		T298	9		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T146	1		T97	18		T300	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13471	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T301	1		T165	1		T258	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T129	17		T177	11		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	4		T222	11		T279	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T149	13		T249	7		T278	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1111	1			T80	2		T136	16		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T100	16		T39	13		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T129	10		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T130	4		T38	9		T213	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	9		T39	12		T152	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T260	11		T222	6		T274	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T13	2		T31	1		T275	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T132	2		T302	12		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	8		T193	18		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T129	10		T44	1		T274	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T178	7		T101	9		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	14		T54	4		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T14	2		T259	5		T303	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T279	2		T276	6		T244	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	12		T17	8		T137	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T191	5		T298	8		T304	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T146	14		T97	11		T300	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T301	2		T165	10		T258	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T19	5		T191	14		T279	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T146	1		T151	19		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T41	3		T129	16		T177	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	3		T13	2		T222	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	3		T149	16		T151	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T146	1		T101	1		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	1		T20	10		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	2		T128	12		T129	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T79	1		T130	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	1		T39	12		T152	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T260	1		T222	1		T274	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	3		T40	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T132	11		T138	5		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	1		T286	1		T149	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T54	1		T44	4		T274	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T128	10		T150	8		T193	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T130	1		T129	8		T176	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T42	2		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T150	13		T176	7		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1843	1			T15	15		T17	8		T18	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T191	5		T279	2		T244	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T146	14		T243	8		T239	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T129	17		T177	11		T100	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	4		T222	11		T244	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T43	1		T149	13		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T146	12		T101	10		T134	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T100	16		T39	13		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T128	9		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T130	4		T38	9		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T146	9		T39	12		T152	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T260	11		T222	6		T274	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	2		T31	1		T275	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	2		T302	12		T207	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	8		T149	2		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T54	4		T44	1		T274	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T193	18		T178	7		T101	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T130	14		T129	10		T152	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	2		T259	5		T303	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T177	1		T276	6		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1143	1			T15	12		T17	8		T80	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T129	18		T177	12		T43	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	2		T13	5		T222	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	1		T149	15		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1461	1			T18	2		T80	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	1		T79	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	2		T129	11		T252	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T130	5		T38	10		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	4		T146	10		T39	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T177	1		T260	12		T222	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	3		T131	1		T94	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T132	3		T138	1		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	9		T150	1		T193	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T129	11		T97	1		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T128	1		T42	2		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T130	15		T176	2		T54	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	3		T182	1		T259	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T19	4		T150	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	13		T17	9		T79	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T191	6		T298	9		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T146	15		T97	13		T300	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13576	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T301	3		T165	11		T258	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T129	15		T177	15		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T13	1		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T149	14		T151	3		T249	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1328	1			T46	7		T49	19		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T20	9		T39	10		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	1		T129	15		T294	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	2		T213	8		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	1		T39	11		T152	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T274	2		T200	8		T297	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T94	5		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	10		T138	4		T248	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T150	7		T193	12		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T129	7		T97	10		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T128	9		T134	9		T250	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T176	17		T152	15		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T259	6		T163	11		T270	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T19	1		T150	12		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T15	14		T17	7		T137	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T191	13		T298	8		T305	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T97	16		T300	7		T306	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T41	1		T307	2		T308	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T258	14		T208	16		T309	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T19	4		T191	6		T279	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T146	15		T151	1		T243	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T41	2		T129	18		T177	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	2		T13	5		T222	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T43	3		T149	15		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T146	13		T101	11		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	1		T20	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	2		T128	10		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T79	1		T130	5		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T146	10		T39	13		T152	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T260	12		T222	7		T274	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	3		T40	4		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T132	3		T138	1		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T130	9		T286	1		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T54	5		T44	4		T274	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T128	1		T150	1		T193	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T130	15		T129	11		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	3		T42	2		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T150	1		T176	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1523	1			T15	13		T17	9		T18	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T19	1		T191	13		T279	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T151	18		T209	10		T310	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T41	1		T129	15		T177	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	1		T13	1		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T43	1		T149	14		T151	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	7		T279	15		T203	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T20	9		T39	10		T196	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	1		T128	11		T129	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	2		T213	8		T274	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T39	11		T152	18		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T274	2		T311	17		T297	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	2		T40	1		T94	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T132	10		T138	4		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T149	6		T142	13		T266	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T44	1		T274	2		T265	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T128	9		T150	7		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T129	7		T176	11		T97	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T259	6		T163	11		T303	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T150	12		T176	6		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1463	1			T15	14		T17	7		T46	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3