Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16972

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5784

1

T11

3

T12

3

T13

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16727

1

T1

20

T3

14

T4

20

auto[1]

6029

1

T12

3

T13

6

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T153	1		T280	10		T300	15
values[0]	16	1			T100	11		T312	5		-	-
values[1]	916	1			T11	3		T13	6		T41	3
values[2]	607	1			T146	13		T43	4		T101	11
values[3]	682	1			T12	3		T16	1		T20	10
values[4]	625	1			T79	1		T130	5		T131	1
values[5]	539	1			T13	5		T40	5		T131	1
values[6]	741	1			T130	9		T132	13		T138	5
values[7]	542	1			T128	10		T150	8		T193	31
values[8]	764	1			T14	3		T130	15		T42	2
values[9]	3787	1			T15	27		T17	16		T18	2
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1073	1			T11	3		T13	6		T41	3
values[1]	3023	1			T16	1		T18	2		T80	3
values[2]	720	1			T12	3		T20	10		T131	1
values[3]	590	1			T40	5		T79	1		T130	5
values[4]	613	1			T13	5		T131	1		T177	1
values[5]	641	1			T130	9		T150	8		T132	13
values[6]	651	1			T128	10		T42	2		T129	18
values[7]	680	1			T14	3		T17	16		T130	15
values[8]	924	1			T15	27		T19	5		T79	1
values[9]	313	1			T191	19		T146	15		T97	29
minimum	13528	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T41	3		T129	16		T177	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T11	3		T13	2		T222	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T149	11		T151	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1670	1			T18	2		T80	1		T46	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T20	10		T131	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	2		T129	16		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T79	1		T130	1		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	5		T39	12		T152	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T177	1		T222	1		T274	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	3		T131	1		T94	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	11		T138	5		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	1		T150	8		T193	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T129	8		T54	1		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T128	10		T42	2		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T130	1		T176	7		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T17	8		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T19	5		T150	13		T176	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	15		T79	1		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T191	14		T298	9		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T146	1		T97	18		T151	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13413	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T129	17		T177	11		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	4		T222	11		T279	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T149	11		T249	7		T278	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1103	1			T80	2		T136	16		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T100	16		T149	2		T39	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T129	10		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T130	4		T38	9		T213	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	12		T152	20		T276	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T222	6		T274	4		T297	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T13	2		T31	1		T275	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	2		T260	11		T302	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	8		T193	18		T101	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T129	10		T54	4		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T178	7		T134	9		T250	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T130	14		T177	1		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T14	2		T17	8		T259	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T279	2		T152	5		T276	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	12		T137	5		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T191	5		T298	8		T304	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T146	14		T97	11		T243	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T165	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T153	1		T313	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T280	7		T300	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T100	1		T312	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T41	3		T129	16		T177	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	3		T13	2		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T43	3		T149	16		T151	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T146	1		T101	1		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	1		T20	10		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T128	12		T129	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T79	1		T130	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T146	1		T39	12		T276	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T260	1		T222	1		T274	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	3		T40	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	11		T138	5		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T130	1		T286	1		T149	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T54	1		T44	4		T274	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T128	10		T150	8		T193	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T130	1		T129	8		T176	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T42	2		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T19	5		T150	13		T191	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1922	1			T15	15		T17	8		T18	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T280	3		T300	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T100	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T129	17		T177	11		T275	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	4		T213	9		T222	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T43	1		T149	13		T249	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	12		T101	10		T134	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	9		T39	13		T196	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T128	9		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T130	4		T100	16		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T146	9		T39	12		T276	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T260	11		T222	6		T274	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	2		T31	1		T152	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T132	2		T207	4		T314	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T130	8		T149	2		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T54	4		T44	1		T274	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T193	18		T178	7		T101	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T130	14		T129	10		T152	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	2		T259	5		T303	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T191	5		T177	1		T279	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1212	1			T15	12		T17	8		T80	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T41	2		T129	18		T177	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	2		T13	5		T222	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	1		T149	12		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1451	1			T18	2		T80	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T20	1		T131	1		T100	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	2		T129	11		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T79	1		T130	5		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	4		T39	13		T152	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T177	1		T222	7		T274	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	3		T131	1		T94	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	3		T138	1		T260	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T130	9		T150	1		T193	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	11		T54	5		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T128	1		T42	2		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T130	15		T176	1		T177	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	3		T17	9		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T19	4		T150	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	13		T79	1		T137	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T191	6		T298	9		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T146	15		T97	13		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13517	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T165	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T41	1		T129	15		T177	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	1		T13	1		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T149	10		T151	3		T249	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1322	1			T46	7		T49	19		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	9		T149	4		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	1		T129	15		T294	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	2		T213	8		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	1		T39	11		T152	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T274	2		T200	8		T297	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T94	5		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	10		T138	4		T248	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	7		T193	12		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T129	7		T97	10		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T128	9		T134	9		T250	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T176	6		T164	18		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	7		T259	15		T270	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T19	1		T150	12		T176	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	14		T137	7		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T191	13		T298	8		T315	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T97	16		T151	18		T300	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T153	1		T313	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T280	9		T300	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T100	11		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T41	2		T129	18		T177	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	2		T13	5		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T43	3		T149	15		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T146	13		T101	11		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	1		T20	1		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	2		T128	10		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T79	1		T130	5		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T146	10		T39	13		T276	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T260	12		T222	7		T274	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	3		T40	4		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T132	3		T138	1		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T130	9		T286	1		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T54	5		T44	4		T274	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T128	1		T150	1		T193	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T130	15		T129	11		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	3		T42	2		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T19	4		T150	1		T191	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1597	1			T15	13		T17	9		T18	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T280	1		T300	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T312	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T41	1		T129	15		T177	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T13	1		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	1		T149	14		T151	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T134	7		T279	15		T203	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T20	9		T38	2		T39	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	1		T128	11		T129	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T213	8		T274	10		T141	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T39	11		T241	10		T316	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T274	2		T311	17		T297	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	2		T40	1		T94	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	10		T138	4		T291	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T149	6		T142	13		T284	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T44	1		T274	2		T248	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T128	9		T150	7		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T129	7		T176	11		T97	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T259	6		T163	11		T303	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T19	1		T150	12		T191	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1537	1			T15	14		T17	7		T46	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3