Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19102

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3654

1

T13

5

T15

27

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16772

1

T1

20

T3

14

T4

20

auto[1]

5984

1

T11

3

T14

3

T15

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	55	1			T134	19		T164	36		-	-
values[0]	25	1			T317	1		T302	13		T318	11
values[1]	746	1			T14	3		T131	1		T42	2
values[2]	958	1			T41	3		T128	21		T133	1
values[3]	551	1			T137	13		T133	1		T149	9
values[4]	636	1			T13	5		T15	27		T79	1
values[5]	605	1			T12	3		T130	20		T30	4
values[6]	582	1			T11	3		T128	10		T138	11
values[7]	869	1			T16	1		T20	10		T40	5
values[8]	607	1			T17	16		T129	18		T149	22
values[9]	3612	1			T13	6		T18	2		T19	5
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	962	1			T14	3		T41	3		T128	21
values[1]	963	1			T42	2		T137	13		T177	27
values[2]	563	1			T133	1		T100	17		T135	1
values[3]	610	1			T13	5		T15	27		T130	5
values[4]	568	1			T11	3		T79	1		T130	15
values[5]	811	1			T12	3		T20	10		T40	5
values[6]	3099	1			T16	1		T17	16		T18	2
values[7]	534	1			T129	18		T54	5		T43	4
values[8]	968	1			T13	6		T79	1		T150	13
values[9]	168	1			T19	5		T131	1		T177	2
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	1		T128	12		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T41	3		T129	16		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T137	8		T146	1		T149	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T42	2		T177	16		T97	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T133	1		T135	1		T244	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T100	1		T274	3		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	1		T38	3		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	3		T15	15		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	3		T130	1		T128	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T79	1		T248	13		T319	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	2		T40	5		T129	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T20	10		T191	14		T193	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T17	8		T18	2		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T16	1		T149	16		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T54	1		T43	3		T134	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T129	8		T39	11		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T79	1		T176	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T150	13		T100	1		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T131	1		T266	5		T156	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T19	5		T177	1		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	2		T128	9		T178	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T129	17		T101	9		T141	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	5		T146	12		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T177	11		T97	2		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T244	12		T239	3		T303	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T100	16		T274	3		T255	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T130	4		T38	9		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	2		T15	12		T146	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T130	14		T30	1		T250	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T240	12		T320	4		T321	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T129	10		T97	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T191	5		T193	18		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T17	8		T80	2		T136	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T149	13		T274	10		T275	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T54	4		T43	1		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T129	10		T39	13		T213	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	4		T279	2		T251	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T100	12		T134	9		T39	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T167	2		T309	4		T267	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T177	1		T257	7		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T164	19		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T134	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T318	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T317	1		T302	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T131	1		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T42	2		T129	16		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T128	12		T146	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T41	3		T133	1		T177	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T137	8		T133	1		T149	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T274	3		T255	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	3		T131	1		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	3		T15	15		T79	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	2		T130	2		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	1		T32	2		T276	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	3		T128	10		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T94	6		T164	14		T320	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T40	5		T130	1		T129	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T16	1		T20	10		T191	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	8		T182	1		T203	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T129	8		T149	11		T39	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1773	1			T13	2		T18	2		T79	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T19	5		T150	13		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T164	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T134	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T302	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	2		T178	10		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T129	17		T101	9		T141	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T128	9		T146	12		T222	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T177	11		T97	2		T244	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T137	5		T149	2		T244	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T274	3		T255	1		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T38	9		T260	11		T152	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	2		T15	12		T100	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T130	18		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	14		T32	2		T276	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T97	9		T101	10		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T164	13		T320	4		T321	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T130	8		T129	10		T132	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T191	5		T193	18		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T17	8		T142	1		T209	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T129	10		T149	11		T39	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T13	4		T80	2		T136	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T177	1		T100	12		T222	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T14	3		T128	10		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T41	2		T129	18		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T137	6		T146	13		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T42	2		T177	12		T97	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T133	1		T135	1		T244	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T100	17		T274	4		T255	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T130	5		T38	10		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	3		T15	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	2		T130	15		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T79	1		T248	1		T319	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	2		T40	4		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	1		T191	6		T193	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T17	9		T18	2		T80	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	1		T149	15		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T54	5		T43	3		T134	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T129	11		T39	14		T213	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	5		T79	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T150	1		T100	13		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T131	1		T266	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T19	4		T177	2		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T128	11		T213	8		T264	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T41	1		T129	15		T141	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T137	7		T149	6		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T177	15		T97	7		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T244	9		T303	10		T322	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T274	2		T323	2		T298	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T38	2		T151	21		T152	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	2		T15	14		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T128	9		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T248	12		T240	10		T323	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T40	1		T129	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T20	9		T191	13		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T17	7		T46	7		T49	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T149	14		T274	10		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T43	1		T134	7		T279	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T129	7		T39	10		T259	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T176	6		T279	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T150	12		T134	9		T39	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T266	4		T156	9		T309	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T19	1		T37	1		T166	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T164	18		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T134	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T318	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T317	1		T302	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	3		T131	1		T178	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T42	2		T129	18		T101	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T128	10		T146	13		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T41	2		T133	1		T177	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T137	6		T133	1		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T274	4		T255	2		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	10		T131	1		T260	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	3		T15	13		T79	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	2		T130	20		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	15		T32	4		T276	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	2		T128	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T94	1		T164	14		T320	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	4		T130	9		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T16	1		T20	1		T191	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	9		T182	1		T203	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T129	11		T149	12		T39	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T13	5		T18	2		T79	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T19	4		T150	1		T177	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T164	18		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T134	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T318	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T213	8		T274	2		T264	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	15		T141	13		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T128	11		T222	10		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T41	1		T177	15		T97	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	7		T149	6		T244	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T274	2		T34	1		T273	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T38	2		T151	3		T152	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	2		T15	14		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T30	1		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T259	17		T248	12		T261	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T128	9		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T94	5		T164	13		T324	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	1		T129	15		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T20	9		T191	13		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	7		T203	18		T284	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T129	7		T149	10		T39	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T13	1		T46	7		T49	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T19	1		T150	12		T152	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3