Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19217

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3539

1

T11

3

T12

3

T13

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16975

1

T1

20

T3

14

T4

20

auto[1]

5781

1

T16

1

T17

16

T18

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T15	27		T325	1		T316	5
values[0]	74	1			T222	22		T326	1		T327	7
values[1]	548	1			T79	2		T38	12		T131	1
values[2]	3097	1			T18	2		T19	5		T40	5
values[3]	848	1			T11	3		T13	5		T130	20
values[4]	638	1			T12	3		T13	6		T14	3
values[5]	511	1			T41	3		T128	10		T146	15
values[6]	1073	1			T17	16		T131	1		T132	13
values[7]	638	1			T131	1		T176	7		T96	1
values[8]	660	1			T20	10		T137	13		T129	33
values[9]	1098	1			T130	9		T128	21		T133	2
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	812	1			T40	5		T79	2		T38	12
values[1]	3172	1			T13	5		T18	2		T19	5
values[2]	732	1			T12	3		T130	15		T138	11
values[3]	692	1			T11	3		T13	6		T14	3
values[4]	655	1			T17	16		T131	1		T150	13
values[5]	862	1			T128	10		T132	13		T191	19
values[6]	669	1			T137	13		T176	7		T30	4
values[7]	633	1			T20	10		T131	1		T129	33
values[8]	849	1			T15	27		T128	21		T133	1
values[9]	169	1			T130	9		T133	1		T177	27
minimum	13511	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T79	1		T38	3		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T40	5		T79	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T18	2		T19	5		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	3		T177	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T130	1		T177	1		T97	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	2		T138	11		T97	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	2		T14	1		T41	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	3		T16	1		T94	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T131	1		T150	13		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	8		T42	2		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T128	10		T132	11		T191	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T176	12		T101	1		T151	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	1		T96	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T137	8		T176	7		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	1		T129	16		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	10		T96	1		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T15	15		T133	1		T97	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T128	12		T222	1		T264	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T149	5		T251	1		T296	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T130	1		T133	1		T177	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13413	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T38	9		T129	10		T178	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T243	8		T222	11		T279	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T80	2		T136	16		T130	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	2		T31	1		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T130	14		T177	1		T97	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	1		T97	9		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	4		T14	2		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T100	10		T280	3		T314	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T146	14		T152	5		T164	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	8		T100	16		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T132	2		T191	5		T193	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T101	9		T274	4		T241	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	12		T213	9		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T137	5		T30	1		T279	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	17		T178	7		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T164	13		T328	14		T262	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	12		T44	1		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T128	9		T222	6		T278	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T149	2		T251	13		T296	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T130	8		T177	11		T164	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T15	15		T325	1		T296	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T316	5		T329	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T326	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T222	11		T327	6		T330	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T79	1		T38	3		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T79	1		T135	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T18	2		T19	5		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	5		T177	1		T141	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T130	2		T138	5		T97	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	3		T13	3		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	2		T14	1		T150	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	2		T16	1		T42	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T41	3		T128	10		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T182	1		T331	1		T248	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T131	1		T132	11		T191	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T17	8		T176	12		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T131	1		T96	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T176	7		T182	1		T279	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	16		T178	1		T146	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	10		T137	8		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T133	1		T97	11		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T130	1		T128	12		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T15	12		T296	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T329	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T222	11		T327	1		T330	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T38	9		T178	3		T275	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T243	8		T279	12		T249	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T80	2		T136	16		T175	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	12		T242	9		T259	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T130	18		T97	2		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T149	11		T39	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	4		T14	2		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	1		T97	9		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	14		T152	25		T255	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T280	3		T155	2		T332	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T132	2		T191	5		T193	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T17	8		T100	16		T101	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T213	9		T143	11		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T279	2		T274	4		T32	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T129	17		T178	7		T146	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	5		T30	1		T244	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	1		T134	2		T149	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T130	8		T128	9		T177	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T79	1		T38	10		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	4		T79	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T18	2		T19	4		T80	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	3		T177	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T130	15		T177	2		T97	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	2		T138	1		T97	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	5		T14	3		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	2		T16	1		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T131	1		T150	1		T146	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	9		T42	2		T100	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T128	1		T132	3		T191	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T176	1		T101	10		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T146	13		T96	1		T213	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T137	6		T176	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T131	1		T129	18		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T20	1		T96	1		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	13		T133	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T128	10		T222	7		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T149	3		T251	14		T296	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T130	9		T133	1		T177	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13511	1			T1	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	2		T150	7		T129	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	1		T222	10		T279	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T19	1		T46	7		T49	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	2		T31	1		T242	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T97	7		T259	17		T284	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T138	10		T97	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T41	1		T129	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T94	5		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T150	12		T152	15		T196	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	7		T39	11		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T128	9		T132	10		T191	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T176	11		T151	3		T274	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	9		T209	10		T297	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	7		T176	6		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T129	15		T274	2		T244	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	9		T163	11		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	14		T97	10		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T128	11		T264	10		T263	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T149	4		T296	9		T185	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T177	15		T164	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T15	13		T325	1		T296	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T316	1		T329	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T326	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T222	12		T327	6		T330	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T79	1		T38	10		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T79	1		T135	1		T243	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T18	2		T19	4		T80	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	4		T177	1		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T130	20		T138	1		T97	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	2		T13	3		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	5		T14	3		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	2		T16	1		T42	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	2		T128	1		T146	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T182	1		T331	1		T248	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T131	1		T132	3		T191	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T17	9		T176	1		T100	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T131	1		T96	1		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T176	1		T182	1		T279	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T129	18		T178	8		T146	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T20	1		T137	6		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T133	1		T97	1		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T130	9		T128	10		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T15	14		T296	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T316	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T222	10		T327	1		T330	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	2		T150	7		T278	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T279	15		T249	5		T333	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T19	1		T46	7		T49	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	1		T141	13		T242	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T138	4		T97	7		T149	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	1		T13	2		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T150	12		T129	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T94	5		T97	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T41	1		T128	9		T152	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T248	12		T280	1		T322	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T132	10		T191	13		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T17	7		T176	11		T39	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T143	9		T209	10		T297	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T176	6		T279	8		T274	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	15		T274	2		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	9		T137	7		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T97	10		T44	1		T134	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T128	11		T177	15		T264	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3