Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19096

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3660

1

T13

6

T16

1

T17

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16482

1

T1

20

T3

14

T4

20

auto[1]

6274

1

T11

3

T13

6

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T134	19		T152	21		T274	6
values[0]	29	1			T131	1		T139	1		T91	1
values[1]	686	1			T130	15		T146	13		T149	7
values[2]	733	1			T19	5		T40	5		T176	12
values[3]	619	1			T11	3		T12	3		T130	5
values[4]	747	1			T14	3		T17	16		T128	21
values[5]	3054	1			T15	27		T18	2		T80	3
values[6]	657	1			T13	11		T79	1		T131	1
values[7]	508	1			T130	9		T150	8		T129	59
values[8]	731	1			T131	1		T177	1		T97	19
values[9]	1435	1			T16	1		T20	10		T79	1
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	855	1			T130	15		T131	1		T176	12
values[1]	711	1			T19	5		T40	5		T54	5
values[2]	667	1			T11	3		T12	3		T130	5
values[3]	3087	1			T14	3		T17	16		T18	2
values[4]	723	1			T15	27		T79	1		T131	1
values[5]	621	1			T13	11		T129	59		T97	10
values[6]	582	1			T130	9		T150	8		T178	8
values[7]	609	1			T16	1		T131	1		T137	13
values[8]	1140	1			T20	10		T79	1		T42	2
values[9]	202	1			T138	11		T39	24		T213	10
minimum	13559	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T130	1		T146	1		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T131	1		T176	12		T43	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	5		T54	1		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	5		T133	1		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	3		T12	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T41	3		T38	3		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T14	1		T18	2		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	8		T128	12		T191	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	15		T79	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T131	1		T193	13		T279	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	3		T129	16		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	2		T129	16		T97	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T130	1		T293	1		T265	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T150	8		T178	1		T94	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T177	1		T97	10		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T16	1		T131	1		T137	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T20	10		T79	1		T129	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T42	2		T132	11		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T39	11		T213	1		T242	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T138	11		T334	1		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T336	2		T337	15		T338	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	14		T146	12		T251	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T43	1		T100	16		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T54	4		T39	12		T244	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T244	7		T301	2		T164	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T130	4		T146	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	9		T30	1		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T14	2		T80	2		T136	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T17	8		T128	9		T191	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	12		T178	3		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T193	18		T279	2		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	2		T129	10		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	4		T129	17		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T130	8		T295	9		T339	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T178	7		T44	1		T222	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T97	9		T100	12		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T137	5		T276	10		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T129	10		T100	10		T101	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T132	2		T146	9		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T39	13		T213	9		T242	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T335	7		T309	4		T267	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T336	7		T338	6		T340	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T134	10		T152	16		T274	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T91	1		T271	1		T341	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T131	1		T139	1		T342	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T130	1		T146	1		T163	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T149	5		T276	1		T288	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	5		T96	1		T286	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	5		T176	12		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	3		T12	2		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	3		T38	3		T150	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T176	7		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	8		T128	12		T191	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T15	15		T18	2		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T193	13		T279	25		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	3		T79	1		T177	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	2		T131	1		T97	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T130	1		T129	16		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	8		T129	16		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T177	1		T97	10		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	1		T44	4		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T20	10		T79	1		T129	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T16	1		T42	2		T137	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T134	9		T152	5		T274	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T271	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T342	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	14		T146	12		T343	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T149	2		T276	6		T288	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T251	13		T244	11		T320	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	1		T100	16		T244	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T130	4		T54	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T38	9		T30	1		T239	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	2		T149	13		T274	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	8		T128	9		T191	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T15	12		T80	2		T136	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T193	18		T279	14		T275	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	2		T177	11		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	4		T97	2		T101	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T130	8		T129	10		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T129	17		T178	7		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T97	9		T100	12		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	1		T141	10		T276	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T129	10		T100	10		T101	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T137	5		T132	2		T146	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T130	15		T146	13		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T131	1		T176	1		T43	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T19	4		T54	5		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	4		T133	1		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	2		T12	2		T130	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T41	2		T38	10		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T14	3		T18	2		T80	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	9		T128	10		T191	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	13		T79	1		T178	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T131	1		T193	19		T279	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	3		T129	11		T260	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	5		T129	18		T97	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T130	9		T293	1		T265	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	1		T178	8		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T177	1		T97	10		T100	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	1		T131	1		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T20	1		T79	1		T129	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T42	2		T132	3		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T39	14		T213	10		T242	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T138	1		T334	1		T335	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T336	8		T337	1		T338	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T163	11		T343	16		T207	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T176	11		T43	1		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	1		T39	11		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	1		T203	18		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	1		T12	1		T138	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T41	1		T38	2		T150	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T46	7		T49	19		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	7		T128	11		T191	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	14		T177	15		T270	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T193	12		T279	8		T263	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	2		T129	15		T134	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T129	15		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T265	11		T295	5		T339	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	7		T94	5		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T97	9		T151	18		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T137	7		T285	9		T344	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T20	9		T129	7		T152	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T132	10		T134	9		T250	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T39	10		T242	11		T266	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T138	10		T345	15		T309	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T336	1		T337	14		T338	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T134	10		T152	6		T274	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T91	1		T271	4		T341	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T131	1		T139	1		T342	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T130	15		T146	13		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T149	3		T276	7		T288	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T19	4		T96	1		T286	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T40	4		T176	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	2		T12	2		T130	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	2		T38	10		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	3		T176	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	9		T128	10		T191	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T15	13		T18	2		T80	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T193	19		T279	16		T275	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	3		T79	1		T177	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	5		T131	1		T97	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T130	9		T129	11		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	1		T129	18		T178	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T177	1		T97	10		T100	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T131	1		T44	4		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	410	1			T20	1		T79	1		T129	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T16	1		T42	2		T137	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T134	9		T152	15		T274	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T341	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T163	11		T343	16		T209	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T149	4		T346	5		T209	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T19	1		T244	10		T273	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	1		T176	11		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	1		T12	1		T138	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T41	1		T38	2		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T176	6		T149	16		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	7		T128	11		T191	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T15	14		T46	7		T49	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T193	12		T279	23		T244	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	2		T177	15		T134	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T97	7		T263	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T129	15		T31	1		T291	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T150	7		T129	15		T94	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T97	9		T151	18		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	1		T141	10		T261	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T20	9		T129	7		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T137	7		T132	10		T138	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3