Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22756

1

T1

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19050

1

T1

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3706

1

T13

6

T15

27

T40

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16453

1

T1

20

T3

14

T4

20

auto[1]

6303

1

T11

3

T13

6

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18723

1

T1

20

T3

14

T4

20

auto[1]

4033

1

T5

2

T12

1

T13

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	185	1			T132	13		T152	21		T274	6
values[0]	11	1			T139	1		T342	10		-	-
values[1]	771	1			T130	15		T131	1		T146	13
values[2]	658	1			T19	5		T40	5		T176	12
values[3]	604	1			T11	3		T12	3		T130	5
values[4]	709	1			T14	3		T17	16		T128	21
values[5]	3113	1			T15	27		T18	2		T80	3
values[6]	616	1			T13	11		T79	1		T131	1
values[7]	543	1			T130	9		T150	8		T129	59
values[8]	727	1			T16	1		T131	1		T177	1
values[9]	1309	1			T20	10		T79	1		T42	2
minimum	13510	1			T1	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	642	1			T130	15		T131	1		T176	12
values[1]	777	1			T19	5		T40	5		T38	12
values[2]	638	1			T11	3		T12	3		T130	5
values[3]	3118	1			T14	3		T17	16		T18	2
values[4]	668	1			T15	27		T79	1		T131	1
values[5]	653	1			T13	11		T129	59		T97	10
values[6]	548	1			T130	9		T150	8		T178	8
values[7]	614	1			T16	1		T131	1		T137	13
values[8]	1210	1			T20	10		T79	1		T42	2
values[9]	157	1			T39	24		T213	10		T242	26
minimum	13731	1			T1	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

4315

1

T11

1

T12

1

T13

3

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T130	1		T146	1		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	1		T176	12		T43	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	5		T38	3		T138	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	5		T133	1		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	3		T12	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	3		T150	13		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T14	1		T17	8		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T128	12		T191	14		T193	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T79	1		T178	1		T177	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	15		T131	1		T279	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	3		T129	16		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T129	16		T97	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T130	1		T264	11		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	8		T178	1		T94	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	1		T177	1		T97	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T131	1		T137	8		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T20	10		T79	1		T129	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	434	1			T42	2		T132	11		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T213	1		T242	12		T310	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T39	11		T266	6		T334	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13459	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T139	1		T257	1		T324	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T130	14		T146	12		T207	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	1		T100	16		T276	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T38	9		T54	4		T39	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T244	7		T257	9		T301	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T130	4		T146	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T30	1		T177	1		T239	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T14	2		T17	8		T80	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T128	9		T191	5		T193	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T178	3		T177	11		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	12		T279	2		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	2		T129	10		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	4		T129	17		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T130	8		T141	10		T295	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T178	7		T100	12		T44	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T97	9		T141	12		T242	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T137	5		T276	10		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T129	10		T100	10		T101	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T132	2		T146	9		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T213	9		T242	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T39	13		T266	14		T157	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	2		T16	1		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T257	7		T184	11		T336	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T274	3		T140	1		T347	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T132	11		T152	16		T259	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T139	1		T342	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T130	1		T146	1		T149	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T131	1		T276	1		T288	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	5		T96	1		T286	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T40	5		T176	12		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	3		T12	2		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T41	3		T150	13		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T17	8		T176	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T128	12		T191	14		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T18	2		T80	1		T46	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	15		T193	13		T279	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	3		T79	1		T177	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	2		T131	1		T97	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T130	1		T129	16		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	8		T129	16		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T16	1		T177	1		T97	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T131	1		T100	1		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T20	10		T79	1		T129	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T42	2		T137	8		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13412	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T274	3		T297	4		T155	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T132	2		T152	5		T259	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T342	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T130	14		T146	12		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T276	6		T288	2		T278	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T251	13		T244	11		T320	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	1		T100	16		T244	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T130	4		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T30	1		T239	3		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	2		T17	8		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T128	9		T191	5		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T80	2		T136	16		T175	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	12		T193	18		T279	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	2		T177	11		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	4		T97	2		T101	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T130	8		T129	10		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	17		T178	7		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T97	9		T141	10		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T100	12		T44	1		T276	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T129	10		T100	10		T101	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T137	5		T146	9		T134	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T16	1		T19	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T130	15		T146	13		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T131	1		T176	1		T43	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T19	4		T38	10		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	4		T133	1		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	2		T12	2		T130	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T41	2		T150	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T14	3		T17	9		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T128	10		T191	6		T193	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T79	1		T178	4		T177	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	13		T131	1		T279	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	3		T129	11		T260	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	5		T129	18		T97	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T130	9		T264	1		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	1		T178	8		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	1		T177	1		T97	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T131	1		T137	6		T276	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T20	1		T79	1		T129	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T42	2		T132	3		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T213	10		T242	15		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	14		T266	15		T334	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13551	1			T1	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T139	1		T257	8		T324	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T163	11		T209	6		T207	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T176	11		T43	1		T278	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T19	1		T38	2		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	1		T203	18		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T12	1		T149	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T41	1		T150	12		T30	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T17	7		T46	7		T49	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T128	11		T191	13		T193	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T177	15		T149	10		T200	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	14		T279	8		T263	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	2		T129	15		T134	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T129	15		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T264	10		T141	10		T265	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T150	7		T94	5		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T97	9		T151	18		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T137	7		T266	4		T285	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T20	9		T129	7		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T132	10		T134	9		T152	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T242	11		T310	7		T348	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T39	10		T266	5		T267	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T149	4		T343	16		T349	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T324	12		T350	6		T336	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T274	4		T140	1		T347	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T132	3		T152	6		T259	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T139	1		T342	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T130	15		T146	13		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T131	1		T276	7		T288	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	4		T96	1		T286	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	4		T176	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	2		T12	2		T130	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	2		T150	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	3		T17	9		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T128	10		T191	6		T177	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T18	2		T80	3		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	13		T193	19		T279	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	3		T79	1		T177	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	5		T131	1		T97	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T130	9		T129	11		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T150	1		T129	18		T178	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	1		T177	1		T97	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T131	1		T100	13		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T20	1		T79	1		T129	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T42	2		T137	6		T146	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13510	1			T1	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T274	2		T297	4		T348	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T132	10		T152	15		T259	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T149	4		T163	11		T343	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T278	16		T346	5		T209	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T19	1		T244	10		T282	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	1		T176	11		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T12	1		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T41	1		T150	12		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	7		T176	6		T149	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T128	11		T191	13		T151	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T46	7		T49	19		T128	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	14		T193	12		T279	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	2		T177	15		T134	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T97	7		T263	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T129	15		T31	1		T264	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T150	7		T129	15		T94	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T97	9		T151	18		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T44	1		T261	11		T344	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T20	9		T129	7		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T137	7		T134	9		T39	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18441

1

T1

20

T3

14

T4

20

auto[1]

auto[0]

4315

1

T11

1

T12

1

T13

3