Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5630	1			T3	8		T4	20		T5	3
testmodes[AdcCtrlTestmodeNormal]	4819	1			T3	11		T5	5		T7	10
testmodes[AdcCtrlTestmodeLowpower]	5000	1			T5	2		T6	1		T9	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2790	1			T3	2		T4	19		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1521	1			T3	6		T5	1		T7	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1210	1			T24	1		T43	1		T51	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1537	1			T3	6		T5	2		T7	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1708	1			T3	4		T5	2		T7	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1225	1			T5	1		T9	1		T48	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1187	1			T9	1		T24	1		T51	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1247	1			T5	1		T50	1		T51	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2325	1			T5	1		T9	4		T10	12