Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.14

Total tests in report: 920

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
76.89	76.89	98.36	98.36	83.53	83.53	89.57	89.57	67.57	67.57	97.28	97.28	86.48	86.48	15.42	15.42	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2742855740
80.53	3.64	98.40	0.03	83.57	0.04	89.57	0.00	91.89	24.32	97.40	0.12	86.48	0.00	16.37	0.95	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.513854206
83.84	3.32	98.83	0.43	92.34	8.77	91.00	1.42	91.89	0.00	98.39	0.99	90.48	4.01	23.96	7.59	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2277526303
85.72	1.88	98.83	0.00	92.88	0.54	97.39	6.40	91.89	0.00	98.45	0.06	94.82	4.34	25.80	1.85	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3456644888
87.17	1.45	98.83	0.00	93.37	0.49	97.39	0.00	91.89	0.00	98.58	0.12	94.99	0.17	35.14	9.33	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.245433187
88.27	1.10	98.83	0.00	93.54	0.16	97.39	0.00	91.89	0.00	98.58	0.00	95.66	0.67	42.00	6.86	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.164623570
89.20	0.93	98.83	0.00	93.58	0.04	97.39	0.00	91.89	0.00	98.58	0.00	95.66	0.00	48.44	6.44	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1097286495
90.00	0.80	98.83	0.00	93.58	0.00	97.39	0.00	97.30	5.41	98.58	0.00	95.66	0.00	48.64	0.20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2152718057
90.73	0.74	98.83	0.00	93.58	0.00	97.39	0.00	97.30	0.00	98.58	0.00	95.66	0.00	53.81	5.17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.330990013
91.30	0.56	98.83	0.00	93.58	0.00	97.39	0.00	100.00	2.70	98.58	0.00	95.66	0.00	55.05	1.25	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.276537187
91.85	0.56	98.83	0.00	93.58	0.00	97.39	0.00	100.00	0.00	98.58	0.00	95.66	0.00	58.95	3.89	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1833127292
92.38	0.52	98.83	0.00	93.58	0.00	97.39	0.00	100.00	0.00	98.58	0.00	95.66	0.00	62.59	3.64	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.3467577056
92.83	0.45	98.86	0.03	93.74	0.16	99.53	2.13	100.00	0.00	98.64	0.06	96.33	0.67	62.72	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.446801236
93.22	0.39	98.86	0.00	93.74	0.00	99.53	0.00	100.00	0.00	98.64	0.00	96.33	0.00	65.46	2.75	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.335312593
93.58	0.36	98.92	0.06	94.44	0.70	99.53	0.00	100.00	0.00	98.70	0.06	96.49	0.17	66.96	1.50	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1243978653
93.92	0.34	98.92	0.00	94.44	0.00	99.53	0.00	100.00	0.00	98.70	0.00	96.49	0.00	69.35	2.40	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3220032364
94.21	0.29	98.92	0.00	95.72	1.28	99.53	0.00	100.00	0.00	98.70	0.00	96.83	0.33	69.75	0.40	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2281148887
94.48	0.28	98.92	0.00	95.72	0.00	99.53	0.00	100.00	0.00	98.70	0.00	96.83	0.00	71.70	1.95	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2544364112
94.73	0.25	98.92	0.00	95.72	0.00	99.53	0.00	100.00	0.00	98.70	0.00	96.83	0.00	73.45	1.75	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.911167688
94.94	0.20	98.92	0.00	95.92	0.21	99.53	0.00	100.00	0.00	98.70	0.00	96.83	0.00	74.67	1.22	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1021992520
95.13	0.19	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.16	1.34	74.67	0.00	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.974245772
95.30	0.17	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.16	0.00	75.89	1.22	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1317568988
95.48	0.17	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.16	0.00	77.09	1.20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2089521056
95.62	0.15	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.16	0.00	78.11	1.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.492987837
95.75	0.13	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.17	78.84	0.72	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.4075164144
95.87	0.12	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	79.66	0.82	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.4020759924
95.97	0.10	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	80.36	0.70	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.3022499031
96.06	0.09	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	81.01	0.65	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3300072151
96.14	0.08	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	81.58	0.57	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3179456223
96.22	0.08	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	82.16	0.57	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1164686491
96.30	0.08	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	82.71	0.55	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.340448820
96.38	0.07	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	83.23	0.52	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4220612296
96.45	0.07	98.92	0.00	95.92	0.00	99.53	0.00	100.00	0.00	98.70	0.00	98.33	0.00	83.73	0.50	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.334435156
96.51	0.06	99.01	0.09	96.05	0.12	99.76	0.24	100.00	0.00	98.70	0.00	98.33	0.00	83.73	0.00	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1329213226
96.58	0.06	99.01	0.00	96.05	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	84.18	0.45	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.342237591
96.64	0.06	99.01	0.00	96.29	0.25	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	84.38	0.20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3116659324
96.70	0.06	99.07	0.06	96.54	0.25	99.76	0.00	100.00	0.00	98.83	0.12	98.33	0.00	84.38	0.00	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2140982547
96.76	0.05	99.07	0.00	96.54	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	84.75	0.37	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.238491492
96.81	0.05	99.07	0.00	96.54	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.13	0.37	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.1104740744
96.86	0.05	99.07	0.00	96.54	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.48	0.35	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.1953746710
96.91	0.05	99.07	0.00	96.54	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.80	0.32	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.24958977
96.95	0.05	99.07	0.00	96.54	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.12	0.32	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.1029252165
96.99	0.04	99.07	0.00	96.54	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.42	0.30	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.969151337
97.04	0.04	99.07	0.00	96.54	0.00	100.00	0.24	100.00	0.00	98.83	0.00	98.33	0.00	86.47	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.729104863
97.07	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.70	0.22	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.2554786423
97.10	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.92	0.22	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.1853961651
97.13	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.12	0.20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3819397088
97.16	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.32	0.20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.559073623
97.18	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.52	0.20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.1309553021
97.21	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.70	0.17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.648782390
97.23	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.87	0.17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.4208808896
97.26	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.05	0.17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.2397805097
97.28	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.22	0.17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.3212783483
97.31	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.40	0.17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1326073639
97.33	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.55	0.15	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.435406441
97.35	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.69	0.15	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.1528328255
97.37	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.82	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.127159009
97.39	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.94	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.528358850
97.41	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.07	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3124303925
97.42	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.19	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1539310784
97.44	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.32	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.3909720902
97.46	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.44	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.383170622
97.48	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.57	0.12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1220011365
97.49	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.67	0.10	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.1805953387
97.50	0.01	99.07	0.00	96.62	0.08	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.67	0.00	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3386027842
97.51	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.74	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.955051991
97.52	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.82	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3628789058
97.54	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.89	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.1254950435
97.55	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.97	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.416003311
97.56	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.04	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1528342002
97.57	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.12	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.3576159126
97.58	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.19	0.07	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.303042981
97.59	0.01	99.07	0.00	96.67	0.04	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.22	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2573294341
97.59	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.27	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.843386969
97.60	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.32	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.795901640
97.61	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.37	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1526621070
97.62	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.42	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3901362641
97.62	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.47	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.360992228
97.63	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.52	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.2725638155
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.57	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4228385545
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.62	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4022738193
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.67	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3074465232
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.72	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.4213949118
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.77	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2740652055
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.82	0.05	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.767666972
97.68	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.84	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3464232936
97.68	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.87	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1060630184
97.68	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.89	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.553748055
97.69	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.92	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.1534985463
97.69	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.94	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1351750423
97.69	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.97	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2984757302
97.70	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.99	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2684081896
97.70	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.02	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.3416691441
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.04	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.579569388
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.07	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.3248458075
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.09	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.1628591508
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.12	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.2634990041
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.14	0.02	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.3785840239

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1823144513
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1604949847
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.462948686
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1699255480
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.3256097004
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.849544023
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1102746653
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1801321086
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2461632022
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2528499672
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3832281137
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3132495426
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3327773655
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4220244099
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4251424803
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.310896835
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4255122782
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3160235682
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.415123989
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3859328636
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3260132836
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1154091074
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.101632441
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2804294115
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2978285262
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.78120166
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1172052299
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3748752713
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3363442398
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.1185557374
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.463870911
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.895938342
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3328767629
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2368128340
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1246136180
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1396650821
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.53202744
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.820810860
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1153018188
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2754253359
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.810576904
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3318803251
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1033242823
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1484556191
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.855202740
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3235071916
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.827559821
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3274843182
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2203065594
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2493484681
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1281718420
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3468990399
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2367965024
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3229846510
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2170755938
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1751001522
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3848907638
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2527765591
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1518282573
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3896861255
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3876214312
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2712740200
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1003749286
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.765736868
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4206269040
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.648373443
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.528448232
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3866567406
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/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.117725768
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2173666236
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.290840244
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1951863928
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1958721449
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3569329456
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2897166535
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.4119838800
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2799522879
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.694321090
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3241439469
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.620648518
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2878899074
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2891012399
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2374747352
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.87002781
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.512655661
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3779672487
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1750860877
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.4292231958
/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.602831242

---

Total test records in report: 920

---

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1329213226			Sep 09 05:19:08 AM UTC 24	Sep 09 05:19:10 AM UTC 24	348237477 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.446801236			Sep 09 05:19:07 AM UTC 24	Sep 09 05:19:12 AM UTC 24	8224437838 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3857132745			Sep 09 05:19:05 AM UTC 24	Sep 09 05:19:15 AM UTC 24	4961008031 ps
T21	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.281113775			Sep 09 05:19:16 AM UTC 24	Sep 09 05:19:18 AM UTC 24	446825652 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3961887266			Sep 09 05:19:04 AM UTC 24	Sep 09 05:19:18 AM UTC 24	5606501357 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2742855740			Sep 09 05:19:07 AM UTC 24	Sep 09 05:19:20 AM UTC 24	17585185415 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.729104863			Sep 09 05:20:31 AM UTC 24	Sep 09 05:25:35 AM UTC 24	175944188776 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3270713918			Sep 09 05:26:02 AM UTC 24	Sep 09 05:26:06 AM UTC 24	5100156865 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3330243276			Sep 09 05:19:16 AM UTC 24	Sep 09 05:19:22 AM UTC 24	5672505231 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.513142339			Sep 09 05:19:13 AM UTC 24	Sep 09 05:19:22 AM UTC 24	17062644733 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2662878823			Sep 09 05:19:05 AM UTC 24	Sep 09 05:19:27 AM UTC 24	29503653508 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.478149797			Sep 09 05:19:12 AM UTC 24	Sep 09 05:19:28 AM UTC 24	4105287012 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.2315197688			Sep 09 05:19:08 AM UTC 24	Sep 09 05:19:29 AM UTC 24	6011976764 ps
T22	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.24217586			Sep 09 05:19:28 AM UTC 24	Sep 09 05:19:34 AM UTC 24	3443575978 ps
T23	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3997655559			Sep 09 05:19:13 AM UTC 24	Sep 09 05:19:36 AM UTC 24	4551162150 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.3773200008			Sep 09 05:19:36 AM UTC 24	Sep 09 05:19:39 AM UTC 24	330495445 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.2657490638			Sep 09 05:19:13 AM UTC 24	Sep 09 05:19:40 AM UTC 24	38102810708 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.177263009			Sep 09 05:19:35 AM UTC 24	Sep 09 05:19:41 AM UTC 24	7852158939 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.593875550			Sep 09 05:19:30 AM UTC 24	Sep 09 05:19:47 AM UTC 24	2759791739 ps
T140	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3501729181			Sep 09 05:19:36 AM UTC 24	Sep 09 05:19:57 AM UTC 24	5875467019 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2437227658			Sep 09 05:19:55 AM UTC 24	Sep 09 05:20:04 AM UTC 24	3091098593 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.2317614040			Sep 09 05:19:33 AM UTC 24	Sep 09 05:20:13 AM UTC 24	9629195194 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.3647113088			Sep 09 05:19:58 AM UTC 24	Sep 09 05:20:18 AM UTC 24	35395709483 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.1174041283			Sep 09 05:19:08 AM UTC 24	Sep 09 05:20:19 AM UTC 24	331116324413 ps
T141	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.3860614048			Sep 09 05:20:19 AM UTC 24	Sep 09 05:20:23 AM UTC 24	467777168 ps
T142	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1520890319			Sep 09 05:19:28 AM UTC 24	Sep 09 05:20:23 AM UTC 24	25527148811 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3456644888			Sep 09 05:20:06 AM UTC 24	Sep 09 05:20:29 AM UTC 24	3328608902 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2035230875			Sep 09 05:20:19 AM UTC 24	Sep 09 05:20:31 AM UTC 24	4702946307 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2209166691			Sep 09 05:19:40 AM UTC 24	Sep 09 05:20:49 AM UTC 24	165440754418 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.893337934			Sep 09 05:20:21 AM UTC 24	Sep 09 05:20:52 AM UTC 24	5582518505 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1023288637			Sep 09 05:20:50 AM UTC 24	Sep 09 05:20:54 AM UTC 24	3692521248 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2352470715			Sep 09 05:19:04 AM UTC 24	Sep 09 05:20:54 AM UTC 24	168581028174 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.2626402919			Sep 09 05:20:59 AM UTC 24	Sep 09 05:21:03 AM UTC 24	405121452 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3321518026			Sep 09 05:20:54 AM UTC 24	Sep 09 05:21:04 AM UTC 24	4158312202 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.1008717356			Sep 09 05:20:52 AM UTC 24	Sep 09 05:21:14 AM UTC 24	34994169118 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.142179417			Sep 09 05:19:40 AM UTC 24	Sep 09 05:21:20 AM UTC 24	167150664584 ps
T84	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1438280795			Sep 09 05:20:58 AM UTC 24	Sep 09 05:21:24 AM UTC 24	4655267957 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1311385219			Sep 09 05:19:05 AM UTC 24	Sep 09 05:21:26 AM UTC 24	206982042483 ps
T381	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.3488227746			Sep 09 05:21:04 AM UTC 24	Sep 09 05:21:29 AM UTC 24	5876981965 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2277526303			Sep 09 05:19:20 AM UTC 24	Sep 09 05:21:45 AM UTC 24	484090399356 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1243978653			Sep 09 05:19:09 AM UTC 24	Sep 09 05:22:12 AM UTC 24	199835710855 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.340448820			Sep 09 05:19:20 AM UTC 24	Sep 09 05:22:17 AM UTC 24	172300358771 ps
T167	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.1752385875			Sep 09 05:22:13 AM UTC 24	Sep 09 05:22:26 AM UTC 24	2913495527 ps
T85	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3911800409			Sep 09 05:19:09 AM UTC 24	Sep 09 05:22:44 AM UTC 24	160790936294 ps
T129	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.1267091291			Sep 09 05:21:15 AM UTC 24	Sep 09 05:22:46 AM UTC 24	485470727881 ps
T168	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.1158828012			Sep 09 05:22:47 AM UTC 24	Sep 09 05:22:51 AM UTC 24	423270482 ps
T169	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2679761308			Sep 09 05:22:52 AM UTC 24	Sep 09 05:22:56 AM UTC 24	5991076051 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1124924875			Sep 09 05:19:42 AM UTC 24	Sep 09 05:23:17 AM UTC 24	344790754236 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1553596025			Sep 09 05:19:12 AM UTC 24	Sep 09 05:23:28 AM UTC 24	165860911078 ps
T174	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3410463181			Sep 09 05:20:24 AM UTC 24	Sep 09 05:23:30 AM UTC 24	329522509486 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.164623570			Sep 09 05:19:24 AM UTC 24	Sep 09 05:23:37 AM UTC 24	526055885592 ps
T153	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.633134849			Sep 09 05:21:25 AM UTC 24	Sep 09 05:23:40 AM UTC 24	156956175839 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1021992520			Sep 09 05:22:27 AM UTC 24	Sep 09 05:23:41 AM UTC 24	195639073357 ps
T154	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.1774944850			Sep 09 05:23:42 AM UTC 24	Sep 09 05:23:54 AM UTC 24	3022628608 ps
T155	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.204778632			Sep 09 05:22:17 AM UTC 24	Sep 09 05:23:56 AM UTC 24	24239902968 ps
T146	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2323602062			Sep 09 05:20:29 AM UTC 24	Sep 09 05:24:20 AM UTC 24	165263075022 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.276537187			Sep 09 05:24:21 AM UTC 24	Sep 09 05:24:35 AM UTC 24	2878830729 ps
T156	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.4156909167			Sep 09 05:24:37 AM UTC 24	Sep 09 05:24:39 AM UTC 24	477167625 ps
T157	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.4032482648			Sep 09 05:24:40 AM UTC 24	Sep 09 05:24:49 AM UTC 24	5908876497 ps
T130	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4043075132			Sep 09 05:19:22 AM UTC 24	Sep 09 05:24:55 AM UTC 24	597552934340 ps
T230	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.1142712245			Sep 09 05:19:08 AM UTC 24	Sep 09 05:24:58 AM UTC 24	161782430581 ps
T261	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1748285482			Sep 09 05:23:35 AM UTC 24	Sep 09 05:25:06 AM UTC 24	392620522176 ps
T189	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2001837390			Sep 09 05:19:20 AM UTC 24	Sep 09 05:25:12 AM UTC 24	326621149128 ps
T134	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.4020759924			Sep 09 05:21:30 AM UTC 24	Sep 09 05:25:16 AM UTC 24	346859768588 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.513854206			Sep 09 05:19:07 AM UTC 24	Sep 09 05:25:16 AM UTC 24	77425777547 ps
T229	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2646084167			Sep 09 05:23:41 AM UTC 24	Sep 09 05:26:01 AM UTC 24	165149174406 ps
T382	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.149117748			Sep 09 05:23:28 AM UTC 24	Sep 09 05:26:09 AM UTC 24	159780261573 ps
T135	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.499226975			Sep 09 05:19:22 AM UTC 24	Sep 09 05:26:14 AM UTC 24	595222981863 ps
T200	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3691762281			Sep 09 05:26:07 AM UTC 24	Sep 09 05:26:33 AM UTC 24	44752282212 ps
T201	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.3922694258			Sep 09 05:26:33 AM UTC 24	Sep 09 05:26:37 AM UTC 24	489715057 ps
T202	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2652795625			Sep 09 05:19:38 AM UTC 24	Sep 09 05:26:38 AM UTC 24	325807313868 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3246344999			Sep 09 05:26:15 AM UTC 24	Sep 09 05:26:40 AM UTC 24	8757050758 ps
T136	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.245433187			Sep 09 05:19:48 AM UTC 24	Sep 09 05:26:41 AM UTC 24	497573357134 ps
T203	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1958721449			Sep 09 05:26:38 AM UTC 24	Sep 09 05:26:45 AM UTC 24	5589160977 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.1439116233			Sep 09 05:19:30 AM UTC 24	Sep 09 05:26:53 AM UTC 24	85691346719 ps
T204	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.3248508208			Sep 09 05:19:04 AM UTC 24	Sep 09 05:26:57 AM UTC 24	334049584330 ps
T205	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3583913988			Sep 09 05:23:55 AM UTC 24	Sep 09 05:27:14 AM UTC 24	42153012501 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.843386969			Sep 09 05:19:13 AM UTC 24	Sep 09 05:27:17 AM UTC 24	81742385133 ps
T383	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1951863928			Sep 09 05:27:17 AM UTC 24	Sep 09 05:27:25 AM UTC 24	3224797083 ps
T384	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.822759446			Sep 09 05:19:20 AM UTC 24	Sep 09 05:27:36 AM UTC 24	499431136499 ps
T137	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2180373342			Sep 09 05:23:30 AM UTC 24	Sep 09 05:28:06 AM UTC 24	385338446857 ps
T385	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.608781151			Sep 09 05:28:07 AM UTC 24	Sep 09 05:28:10 AM UTC 24	464564284 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2897166535			Sep 09 05:27:38 AM UTC 24	Sep 09 05:28:11 AM UTC 24	32632607429 ps
T138	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1539310784			Sep 09 05:19:40 AM UTC 24	Sep 09 05:28:17 AM UTC 24	369452567716 ps
T147	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4220612296			Sep 09 05:23:18 AM UTC 24	Sep 09 05:28:24 AM UTC 24	497808713837 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2074908537			Sep 09 05:22:18 AM UTC 24	Sep 09 05:28:31 AM UTC 24	76575286099 ps
T386	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.290840244			Sep 09 05:27:18 AM UTC 24	Sep 09 05:28:32 AM UTC 24	37015119625 ps
T139	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.955051991			Sep 09 05:19:04 AM UTC 24	Sep 09 05:28:35 AM UTC 24	501840712265 ps
T235	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1847968537			Sep 09 05:25:14 AM UTC 24	Sep 09 05:28:37 AM UTC 24	211427631761 ps
T387	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1750860877			Sep 09 05:28:10 AM UTC 24	Sep 09 05:28:37 AM UTC 24	5872361620 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1686510970			Sep 09 05:20:53 AM UTC 24	Sep 09 05:28:40 AM UTC 24	97259642073 ps
T158	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3517760426			Sep 09 05:21:27 AM UTC 24	Sep 09 05:28:43 AM UTC 24	352678380976 ps
T388	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3779672487			Sep 09 05:28:40 AM UTC 24	Sep 09 05:28:57 AM UTC 24	4126521374 ps
T131	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.884943061			Sep 09 05:19:12 AM UTC 24	Sep 09 05:29:02 AM UTC 24	191357219094 ps
T389	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.512655661			Sep 09 05:28:44 AM UTC 24	Sep 09 05:29:12 AM UTC 24	42079505549 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.602831242			Sep 09 05:29:03 AM UTC 24	Sep 09 05:29:16 AM UTC 24	7002793044 ps
T390	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.4119838800			Sep 09 05:29:17 AM UTC 24	Sep 09 05:29:20 AM UTC 24	325978568 ps
T266	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2446576406			Sep 09 05:19:36 AM UTC 24	Sep 09 05:29:24 AM UTC 24	167270414471 ps
T391	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1453332328			Sep 09 05:25:17 AM UTC 24	Sep 09 05:29:27 AM UTC 24	198803458486 ps
T392	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.2055832937			Sep 09 05:29:21 AM UTC 24	Sep 09 05:29:29 AM UTC 24	5561786851 ps
T300	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.636526180			Sep 09 05:20:23 AM UTC 24	Sep 09 05:29:31 AM UTC 24	166458808513 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1170060714			Sep 09 05:20:06 AM UTC 24	Sep 09 05:29:31 AM UTC 24	90612531816 ps
T393	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3819397088			Sep 09 05:19:05 AM UTC 24	Sep 09 05:29:41 AM UTC 24	160676809113 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.3719744930			Sep 09 05:21:05 AM UTC 24	Sep 09 05:29:48 AM UTC 24	497526118900 ps
T144	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.1856884554			Sep 09 05:19:05 AM UTC 24	Sep 09 05:30:00 AM UTC 24	370927637369 ps
T145	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.2534204813			Sep 09 05:29:30 AM UTC 24	Sep 09 05:30:08 AM UTC 24	162268104916 ps
T394	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.679697734			Sep 09 05:30:09 AM UTC 24	Sep 09 05:30:28 AM UTC 24	4295422624 ps
T395	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.4160316742			Sep 09 05:24:56 AM UTC 24	Sep 09 05:30:37 AM UTC 24	158291310530 ps
T396	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3670954287			Sep 09 05:25:07 AM UTC 24	Sep 09 05:30:39 AM UTC 24	481279507949 ps
T244	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3241439469			Sep 09 05:28:25 AM UTC 24	Sep 09 05:30:46 AM UTC 24	162688383967 ps
T397	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1365142017			Sep 09 05:30:29 AM UTC 24	Sep 09 05:30:46 AM UTC 24	24637079497 ps
T398	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.1052586740			Sep 09 05:30:47 AM UTC 24	Sep 09 05:30:49 AM UTC 24	409696011 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3958652437			Sep 09 05:30:40 AM UTC 24	Sep 09 05:30:49 AM UTC 24	1223595172 ps
T162	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.492987837			Sep 09 05:26:42 AM UTC 24	Sep 09 05:30:51 AM UTC 24	486966762809 ps
T259	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2715210798			Sep 09 05:30:00 AM UTC 24	Sep 09 05:31:10 AM UTC 24	182249575467 ps
T399	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.4064315751			Sep 09 05:30:50 AM UTC 24	Sep 09 05:31:17 AM UTC 24	5774298492 ps
T132	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.204403927			Sep 09 05:26:58 AM UTC 24	Sep 09 05:31:34 AM UTC 24	344688243674 ps
T183	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2899373971			Sep 09 05:21:45 AM UTC 24	Sep 09 05:31:36 AM UTC 24	170912925233 ps
T184	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3891593194			Sep 09 05:20:55 AM UTC 24	Sep 09 05:31:42 AM UTC 24	488625746143 ps
T185	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.1519832221			Sep 09 05:27:14 AM UTC 24	Sep 09 05:31:44 AM UTC 24	181206546890 ps
T133	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.3147386005			Sep 09 05:20:46 AM UTC 24	Sep 09 05:32:04 AM UTC 24	207234111663 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2152718057			Sep 09 05:23:57 AM UTC 24	Sep 09 05:32:05 AM UTC 24	92600723531 ps
T186	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.1301841989			Sep 09 05:23:37 AM UTC 24	Sep 09 05:32:12 AM UTC 24	162988445626 ps
T148	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.1285334883			Sep 09 05:20:41 AM UTC 24	Sep 09 05:32:26 AM UTC 24	352270758573 ps
T187	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.2507236051			Sep 09 05:32:05 AM UTC 24	Sep 09 05:32:28 AM UTC 24	5052178575 ps
T188	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.405882904			Sep 09 05:24:49 AM UTC 24	Sep 09 05:32:30 AM UTC 24	162276108977 ps
T159	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2866214094			Sep 09 05:20:14 AM UTC 24	Sep 09 05:32:31 AM UTC 24	505164753118 ps
T234	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3464232936			Sep 09 05:29:48 AM UTC 24	Sep 09 05:32:31 AM UTC 24	169620001347 ps
T400	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2144233263			Sep 09 05:32:28 AM UTC 24	Sep 09 05:32:31 AM UTC 24	404540206 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.480952294			Sep 09 05:32:13 AM UTC 24	Sep 09 05:32:50 AM UTC 24	165581960913 ps
T401	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2671783514			Sep 09 05:32:30 AM UTC 24	Sep 09 05:32:58 AM UTC 24	6159337449 ps
T402	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.620648518			Sep 09 05:28:32 AM UTC 24	Sep 09 05:33:07 AM UTC 24	499939796905 ps
T243	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2799522879			Sep 09 05:28:37 AM UTC 24	Sep 09 05:33:09 AM UTC 24	187283640943 ps
T403	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1777207700			Sep 09 05:32:06 AM UTC 24	Sep 09 05:33:25 AM UTC 24	39968984293 ps
T299	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.21296509			Sep 09 05:26:40 AM UTC 24	Sep 09 05:33:26 AM UTC 24	160013839806 ps
T404	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.3430871237			Sep 09 05:33:27 AM UTC 24	Sep 09 05:33:32 AM UTC 24	4203639132 ps
T405	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.607526176			Sep 09 05:20:31 AM UTC 24	Sep 09 05:33:38 AM UTC 24	331331741693 ps
T149	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2544364112			Sep 09 05:31:34 AM UTC 24	Sep 09 05:33:59 AM UTC 24	596306241025 ps
T406	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.2045817829			Sep 09 05:33:33 AM UTC 24	Sep 09 05:34:05 AM UTC 24	30726804041 ps
T375	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1422621946			Sep 09 05:34:00 AM UTC 24	Sep 09 05:34:08 AM UTC 24	13088426020 ps
T407	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.920760787			Sep 09 05:34:09 AM UTC 24	Sep 09 05:34:11 AM UTC 24	471408108 ps
T160	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3527097378			Sep 09 05:31:17 AM UTC 24	Sep 09 05:34:13 AM UTC 24	327453079213 ps
T150	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.2830782387			Sep 09 05:19:09 AM UTC 24	Sep 09 05:34:18 AM UTC 24	334064391882 ps
T408	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2513105988			Sep 09 05:34:12 AM UTC 24	Sep 09 05:34:21 AM UTC 24	5869367629 ps
T161	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1305207830			Sep 09 05:31:44 AM UTC 24	Sep 09 05:34:33 AM UTC 24	554325814718 ps
T170	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.850404152			Sep 09 05:29:27 AM UTC 24	Sep 09 05:34:41 AM UTC 24	485626270978 ps
T163	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3901362641			Sep 09 05:32:31 AM UTC 24	Sep 09 05:34:45 AM UTC 24	331605294304 ps
T207	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.648782390			Sep 09 05:19:13 AM UTC 24	Sep 09 05:34:51 AM UTC 24	130506370643 ps
T409	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.533203429			Sep 09 05:29:31 AM UTC 24	Sep 09 05:35:06 AM UTC 24	477821179720 ps
T253	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.1027745683			Sep 09 05:31:11 AM UTC 24	Sep 09 05:35:09 AM UTC 24	165621558825 ps
T410	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3336550246			Sep 09 05:35:09 AM UTC 24	Sep 09 05:35:30 AM UTC 24	4779413086 ps
T171	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.2835885103			Sep 09 05:32:32 AM UTC 24	Sep 09 05:35:36 AM UTC 24	496263722333 ps
T225	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.4238171469			Sep 09 05:24:36 AM UTC 24	Sep 09 05:35:40 AM UTC 24	102548514392 ps
T411	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3604046469			Sep 09 05:35:40 AM UTC 24	Sep 09 05:35:49 AM UTC 24	1631052630 ps
T218	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3978489425			Sep 09 05:22:45 AM UTC 24	Sep 09 05:36:03 AM UTC 24	529689637433 ps
T151	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.969151337			Sep 09 05:32:32 AM UTC 24	Sep 09 05:36:04 AM UTC 24	488055208491 ps
T412	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.4086578569			Sep 09 05:36:03 AM UTC 24	Sep 09 05:36:05 AM UTC 24	358223715 ps
T231	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.911167688			Sep 09 05:34:52 AM UTC 24	Sep 09 05:36:12 AM UTC 24	337238629358 ps
T413	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.3697855136			Sep 09 05:36:05 AM UTC 24	Sep 09 05:36:13 AM UTC 24	5715547753 ps
T414	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.611935632			Sep 09 05:35:30 AM UTC 24	Sep 09 05:36:15 AM UTC 24	40341725746 ps
T415	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3043177087			Sep 09 05:33:08 AM UTC 24	Sep 09 05:36:17 AM UTC 24	190035073826 ps
T416	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.2102240097			Sep 09 05:26:41 AM UTC 24	Sep 09 05:36:24 AM UTC 24	159753748108 ps
T258	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.346986819			Sep 09 05:19:07 AM UTC 24	Sep 09 05:36:44 AM UTC 24	496826452871 ps
T417	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.117725768			Sep 09 05:26:54 AM UTC 24	Sep 09 05:36:46 AM UTC 24	200269013030 ps
T260	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1978826496			Sep 09 05:26:46 AM UTC 24	Sep 09 05:36:51 AM UTC 24	212946080719 ps
T418	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1684975688			Sep 09 05:36:25 AM UTC 24	Sep 09 05:36:52 AM UTC 24	197104306391 ps
T208	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.2894783364			Sep 09 05:30:38 AM UTC 24	Sep 09 05:36:53 AM UTC 24	106378404153 ps
T419	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1745966215			Sep 09 05:30:52 AM UTC 24	Sep 09 05:36:57 AM UTC 24	322597134132 ps
T420	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.852755820			Sep 09 05:36:46 AM UTC 24	Sep 09 05:36:58 AM UTC 24	4618839153 ps
T421	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.4229768400			Sep 09 05:37:00 AM UTC 24	Sep 09 05:37:03 AM UTC 24	295001249 ps
T211	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2173666236			Sep 09 05:27:25 AM UTC 24	Sep 09 05:37:13 AM UTC 24	99680676567 ps
T237	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1351750423			Sep 09 05:36:54 AM UTC 24	Sep 09 05:37:14 AM UTC 24	14505277178 ps
T422	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3144471523			Sep 09 05:37:04 AM UTC 24	Sep 09 05:37:17 AM UTC 24	5546220127 ps
T164	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1833127292			Sep 09 05:19:05 AM UTC 24	Sep 09 05:37:34 AM UTC 24	487032570217 ps
T172	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.4059231601			Sep 09 05:26:29 AM UTC 24	Sep 09 05:38:06 AM UTC 24	317981079800 ps
T219	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.87002781			Sep 09 05:28:59 AM UTC 24	Sep 09 05:38:19 AM UTC 24	113201390977 ps
T423	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.2998111480			Sep 09 05:36:52 AM UTC 24	Sep 09 05:38:28 AM UTC 24	41911296417 ps
T233	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2089521056			Sep 09 05:33:00 AM UTC 24	Sep 09 05:38:38 AM UTC 24	546424376565 ps
T424	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.4009169256			Sep 09 05:36:14 AM UTC 24	Sep 09 05:38:42 AM UTC 24	163770591111 ps
T242	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3115072572			Sep 09 05:31:45 AM UTC 24	Sep 09 05:38:48 AM UTC 24	328119623297 ps
T425	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3525025391			Sep 09 05:21:29 AM UTC 24	Sep 09 05:39:05 AM UTC 24	399777178932 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.3467577056			Sep 09 05:35:07 AM UTC 24	Sep 09 05:39:07 AM UTC 24	550807660472 ps
T426	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1636448888			Sep 09 05:38:43 AM UTC 24	Sep 09 05:39:07 AM UTC 24	5233363833 ps
T427	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1667085644			Sep 09 05:39:08 AM UTC 24	Sep 09 05:39:18 AM UTC 24	2414174892 ps
T428	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.59599973			Sep 09 05:39:19 AM UTC 24	Sep 09 05:39:23 AM UTC 24	411837344 ps
T267	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2301557883			Sep 09 05:19:09 AM UTC 24	Sep 09 05:39:27 AM UTC 24	357059788992 ps
T429	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.1661061202			Sep 09 05:38:49 AM UTC 24	Sep 09 05:39:28 AM UTC 24	42168669983 ps
T270	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2740652055			Sep 09 05:22:57 AM UTC 24	Sep 09 05:39:33 AM UTC 24	496218801772 ps
T197	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3569329456			Sep 09 05:28:03 AM UTC 24	Sep 09 05:39:34 AM UTC 24	342270227014 ps
T430	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2374747352			Sep 09 05:28:35 AM UTC 24	Sep 09 05:39:47 AM UTC 24	613093256416 ps
T232	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.4030769516			Sep 09 05:29:31 AM UTC 24	Sep 09 05:39:50 AM UTC 24	562313414482 ps
T431	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1059927769			Sep 09 05:39:23 AM UTC 24	Sep 09 05:39:52 AM UTC 24	5834443718 ps
T173	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.335312593			Sep 09 05:34:22 AM UTC 24	Sep 09 05:39:53 AM UTC 24	485163402163 ps
T366	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3177565129			Sep 09 05:38:06 AM UTC 24	Sep 09 05:40:05 AM UTC 24	180960781355 ps
T274	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2388160128			Sep 09 05:36:18 AM UTC 24	Sep 09 05:40:09 AM UTC 24	206309921305 ps
T432	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2880735004			Sep 09 05:19:05 AM UTC 24	Sep 09 05:40:16 AM UTC 24	596782399062 ps
T213	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.3246348469			Sep 09 05:26:09 AM UTC 24	Sep 09 05:40:19 AM UTC 24	137624070228 ps
T433	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.3573162759			Sep 09 05:40:06 AM UTC 24	Sep 09 05:40:20 AM UTC 24	4712743476 ps
T239	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3220032364			Sep 09 05:33:10 AM UTC 24	Sep 09 05:40:26 AM UTC 24	492240560009 ps
T434	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1930910085			Sep 09 05:40:27 AM UTC 24	Sep 09 05:40:31 AM UTC 24	530969316 ps
T206	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2984757302			Sep 09 05:40:19 AM UTC 24	Sep 09 05:40:31 AM UTC 24	3964105176 ps
T238	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.330990013			Sep 09 05:19:24 AM UTC 24	Sep 09 05:40:32 AM UTC 24	527678910500 ps
T435	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1598182359			Sep 09 05:34:46 AM UTC 24	Sep 09 05:40:34 AM UTC 24	401878911313 ps
T436	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2690505257			Sep 09 05:40:10 AM UTC 24	Sep 09 05:40:37 AM UTC 24	30651022991 ps
T437	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.340283743			Sep 09 05:40:32 AM UTC 24	Sep 09 05:40:37 AM UTC 24	5989605282 ps
T438	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.261603798			Sep 09 05:26:46 AM UTC 24	Sep 09 05:40:44 AM UTC 24	492302755586 ps
T249	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.1640774577			Sep 09 05:37:18 AM UTC 24	Sep 09 05:41:11 AM UTC 24	164364615665 ps
T439	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1689408419			Sep 09 05:39:27 AM UTC 24	Sep 09 05:41:20 AM UTC 24	165508086130 ps
T271	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1128060635			Sep 09 05:38:28 AM UTC 24	Sep 09 05:41:22 AM UTC 24	341718961857 ps
T440	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.579381727			Sep 09 05:34:18 AM UTC 24	Sep 09 05:41:28 AM UTC 24	167228500689 ps
T441	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.1871113865			Sep 09 05:41:23 AM UTC 24	Sep 09 05:41:29 AM UTC 24	4981148654 ps
T298	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.767666972			Sep 09 05:28:12 AM UTC 24	Sep 09 05:41:36 AM UTC 24	327358306419 ps
T442	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4046378343			Sep 09 05:37:34 AM UTC 24	Sep 09 05:41:37 AM UTC 24	328260095485 ps
T320	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.2554786423			Sep 09 05:41:13 AM UTC 24	Sep 09 05:41:56 AM UTC 24	164377878241 ps
T236	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1097286495			Sep 09 05:34:05 AM UTC 24	Sep 09 05:41:59 AM UTC 24	733642969020 ps
T443	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1105626889			Sep 09 05:41:57 AM UTC 24	Sep 09 05:42:01 AM UTC 24	344057255 ps
T444	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2112910092			Sep 09 05:41:59 AM UTC 24	Sep 09 05:42:04 AM UTC 24	5866222949 ps
T445	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3095130194			Sep 09 05:31:36 AM UTC 24	Sep 09 05:42:05 AM UTC 24	203571609798 ps
T209	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1858950091			Sep 09 05:32:13 AM UTC 24	Sep 09 05:42:11 AM UTC 24	104724754145 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3224329424			Sep 09 05:41:37 AM UTC 24	Sep 09 05:42:17 AM UTC 24	32471049110 ps
T305	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.4046169742			Sep 09 05:40:21 AM UTC 24	Sep 09 05:42:20 AM UTC 24	221344519969 ps
T280	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2284757113			Sep 09 05:39:34 AM UTC 24	Sep 09 05:42:22 AM UTC 24	161630476234 ps
T446	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2878899074			Sep 09 05:28:17 AM UTC 24	Sep 09 05:42:40 AM UTC 24	325110713995 ps
T447	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1792151428			Sep 09 05:41:29 AM UTC 24	Sep 09 05:42:43 AM UTC 24	32371797629 ps
T363	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.660093624			Sep 09 05:39:08 AM UTC 24	Sep 09 05:42:47 AM UTC 24	181162649064 ps
T448	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.3492721084			Sep 09 05:42:44 AM UTC 24	Sep 09 05:42:56 AM UTC 24	5021396259 ps
T302	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2904451653			Sep 09 05:40:38 AM UTC 24	Sep 09 05:42:56 AM UTC 24	175670482089 ps
T210	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.1534985463			Sep 09 05:36:53 AM UTC 24	Sep 09 05:42:59 AM UTC 24	92262357246 ps
T449	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2166993286			Sep 09 05:39:34 AM UTC 24	Sep 09 05:43:00 AM UTC 24	328831458827 ps
T214	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.4292231958			Sep 09 05:29:13 AM UTC 24	Sep 09 05:43:04 AM UTC 24	281371087669 ps
T450	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.2387063153			Sep 09 05:43:01 AM UTC 24	Sep 09 05:43:04 AM UTC 24	422761322 ps
T451	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1152509660			Sep 09 05:40:37 AM UTC 24	Sep 09 05:43:07 AM UTC 24	334431532287 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2526763178			Sep 09 05:42:57 AM UTC 24	Sep 09 05:43:11 AM UTC 24	2797758452 ps
T452	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1580567954			Sep 09 05:43:02 AM UTC 24	Sep 09 05:43:27 AM UTC 24	5885385591 ps
T344	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.204801634			Sep 09 05:25:36 AM UTC 24	Sep 09 05:43:31 AM UTC 24	342501260856 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.553748055			Sep 09 05:35:50 AM UTC 24	Sep 09 05:43:35 AM UTC 24	138187997159 ps
T165	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.694321090			Sep 09 05:28:37 AM UTC 24	Sep 09 05:43:40 AM UTC 24	366612603124 ps
T453	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.1895151625			Sep 09 05:42:04 AM UTC 24	Sep 09 05:43:42 AM UTC 24	320880751575 ps
T454	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.3080254074			Sep 09 05:43:42 AM UTC 24	Sep 09 05:43:48 AM UTC 24	4975082983 ps
T455	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.2246861755			Sep 09 05:42:48 AM UTC 24	Sep 09 05:44:10 AM UTC 24	25399352963 ps
T319	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.3887217292			Sep 09 05:43:05 AM UTC 24	Sep 09 05:44:11 AM UTC 24	164877015025 ps
T291	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2238025390			Sep 09 05:30:50 AM UTC 24	Sep 09 05:44:14 AM UTC 24	329116264841 ps
T456	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1619430297			Sep 09 05:42:12 AM UTC 24	Sep 09 05:44:17 AM UTC 24	164800502820 ps
T342	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.4208808896			Sep 09 05:39:54 AM UTC 24	Sep 09 05:44:18 AM UTC 24	202355136893 ps
T457	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2692085559			Sep 09 05:29:25 AM UTC 24	Sep 09 05:44:19 AM UTC 24	326148370600 ps
T458	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.451712130			Sep 09 05:44:18 AM UTC 24	Sep 09 05:44:21 AM UTC 24	401433773 ps
T459	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.4093849574			Sep 09 05:43:49 AM UTC 24	Sep 09 05:44:22 AM UTC 24	41938667233 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.291318945			Sep 09 05:44:11 AM UTC 24	Sep 09 05:44:23 AM UTC 24	4298015879 ps
T460	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.1722368267			Sep 09 05:44:19 AM UTC 24	Sep 09 05:44:25 AM UTC 24	5903027667 ps
T301	/workspaces/repo/scratch/os_regression_2024_09_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1219327341			Sep 09 05:41:38 AM UTC 24	Sep 09 05:44:32 AM UTC 24	172963233748 ps