Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20049

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3901

1

T5

7

T40

2

T14

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17636

1

T3

19

T4

20

T5

8

auto[1]

6314

1

T5

7

T40

2

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T162	5		T226	1		T178	2
values[0]	49	1			T164	10		T227	14		T228	1
values[1]	729	1			T41	2		T43	6		T144	6
values[2]	614	1			T48	13		T136	12		T137	32
values[3]	829	1			T9	1		T15	9		T25	2
values[4]	746	1			T40	2		T49	3		T136	19
values[5]	865	1			T6	1		T18	14		T229	27
values[6]	625	1			T134	25		T135	4		T44	5
values[7]	569	1			T16	2		T19	1		T50	18
values[8]	709	1			T5	7		T24	2		T14	6
values[9]	3634	1			T13	2		T17	10		T19	2
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	951	1			T41	2		T43	6		T136	12
values[1]	701	1			T48	13		T25	2		T143	1
values[2]	657	1			T9	1		T15	9		T136	19
values[3]	850	1			T40	2		T49	3		T135	9
values[4]	840	1			T6	1		T18	14		T229	27
values[5]	568	1			T16	2		T19	1		T50	18
values[6]	2935	1			T13	2		T14	6		T17	10
values[7]	726	1			T5	7		T230	1		T135	16
values[8]	772	1			T24	2		T19	2		T50	47
values[9]	396	1			T48	17		T134	21		T45	7
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T41	1		T43	5		T136	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T137	15		T132	16		T172	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T48	6		T143	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	2		T231	13		T232	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T136	9		T158	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	1		T147	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T135	9		T131	9		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T40	2		T49	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T18	10		T233	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T229	13		T188	1		T234	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T16	2		T50	12		T134	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T19	1		T44	4		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T13	2		T17	1		T20	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T144	17		T186	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T230	1		T147	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	5		T135	16		T235	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T24	2		T19	2		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	14		T138	10		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T48	10		T236	18		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	11		T45	6		T237	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	1		T43	1		T136	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T132	9		T172	17		T238	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	7		T162	15		T148	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T231	19		T239	12		T240	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	10		T184	5		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	8		T147	10		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T131	16		T184	2		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T49	2		T162	2		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T18	4		T165	9		T241	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T229	14		T234	11		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T50	6		T134	9		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T44	1		T136	10		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T17	9		T85	7		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	5		T186	14		T27	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T148	5		T159	3		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T5	2		T145	13		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	8		T244	2		T162	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	13		T245	8		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T48	7		T236	11		T247	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	10		T45	1		T237	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T162	1		T226	1		T178	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T164	8		T248	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T227	14		T228	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	1		T43	5		T144	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T172	22		T238	14		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	6		T136	8		T137	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T137	15		T132	16		T239	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T9	1		T184	14		T148	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	1		T25	2		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	9		T158	13		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	2		T49	1		T206	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T6	1		T18	10		T135	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T229	13		T149	14		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T134	16		T135	4		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	4		T136	11		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	2		T50	12		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T19	1		T186	12		T233	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T24	2		T230	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	5		T14	1		T135	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1823	1			T13	2		T17	1		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T50	14		T134	11		T45	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T162	4		T250	2		T251	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T164	2		T248	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T41	1		T43	1		T242	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T172	17		T238	15		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	7		T136	4		T162	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T132	9		T239	12		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T184	5		T148	8		T253	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	8		T147	10		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T136	10		T151	11		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	2		T254	6		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T18	4		T131	16		T184	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T229	14		T245	9		T255	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T134	9		T133	18		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T44	1		T136	10		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T50	6		T146	6		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T186	14		T256	4		T257	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T159	3		T258	14		T173	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	2		T14	5		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T17	9		T85	7		T48	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T50	13		T134	10		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T41	2		T43	5		T136	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T137	1		T132	10		T172	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T48	8		T143	1		T162	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T25	2		T231	20		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T136	11		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	9		T147	11		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T135	1		T131	17		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	2		T49	3		T162	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T18	5		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T229	15		T188	1		T234	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	2		T50	7		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	1		T44	4		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T13	2		T17	10		T20	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	6		T144	1		T186	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T230	1		T147	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T5	5		T135	1		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T24	2		T19	2		T50	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T50	14		T138	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T48	8		T236	12		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T134	11		T45	6		T237	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	1		T136	7		T137	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T137	14		T132	15		T172	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T48	5		T259	15		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T231	12		T232	9		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	8		T158	12		T184	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T185	12		T231	12		T260	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	8		T131	8		T233	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T175	6		T241	14		T106	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	9		T233	15		T165	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T229	12		T234	12		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T50	11		T134	15		T135	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T44	1		T136	10		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T20	11		T130	42		T261	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T144	16		T186	11		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T148	1		T164	6		T262	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	2		T135	15		T235	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T50	11		T138	14		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T50	13		T138	9		T158	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T48	9		T236	17		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T134	10		T45	1		T237	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T162	5		T226	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T164	3		T248	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T227	1		T228	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T41	2		T43	5		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T172	18		T238	16		T249	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	8		T136	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T137	1		T132	10		T239	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	1		T184	6		T148	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	9		T25	2		T147	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T136	11		T158	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	2		T49	3		T206	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T18	5		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T229	15		T149	1		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T134	10		T135	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	4		T136	11		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	2		T50	7		T146	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	1		T186	15		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T24	2		T230	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	5		T14	6		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T13	2		T17	10		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T50	14		T134	11		T45	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T178	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T164	7		T248	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T227	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T43	1		T144	5		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T172	21		T238	13		T214	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	5		T136	7		T137	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T137	14		T132	15		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T184	13		T148	10		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T185	12		T231	24		T260	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T136	8		T158	12		T164	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T175	6		T106	6		T195	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T18	9		T135	8		T131	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T229	12		T149	13		T255	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T134	15		T135	3		T133	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T44	1		T136	10		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T50	11		T149	8		T197	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T186	11		T233	9		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T190	18		T246	7		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	2		T135	15		T235	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T20	11		T48	9		T50	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T50	13		T134	10		T45	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20266

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3684

1

T5

7

T9

1

T14

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17472

1

T3

19

T4

20

T5

8

auto[1]

6478

1

T5

7

T40

2

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	298	1			T6	1		T24	1		T51	7
values[0]	2	1			T264	1		T265	1		-	-
values[1]	759	1			T9	1		T19	1		T146	7
values[2]	3007	1			T13	2		T14	6		T17	10
values[3]	637	1			T40	2		T41	2		T135	9
values[4]	821	1			T15	9		T18	14		T48	13
values[5]	745	1			T19	1		T48	17		T50	20
values[6]	786	1			T230	1		T44	5		T144	6
values[7]	676	1			T24	2		T19	1		T49	3
values[8]	651	1			T137	17		T139	2		T185	20
values[9]	1280	1			T5	7		T16	2		T50	45
minimum	14288	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	970	1			T9	1		T19	1		T146	7
values[1]	2991	1			T13	2		T14	6		T17	10
values[2]	583	1			T40	2		T15	9		T48	13
values[3]	899	1			T18	14		T50	20		T131	25
values[4]	748	1			T19	1		T48	17		T43	6
values[5]	646	1			T44	5		T188	1		T149	9
values[6]	716	1			T24	2		T19	1		T49	3
values[7]	713	1			T25	2		T137	17		T266	1
values[8]	844	1			T5	7		T16	2		T50	45
values[9]	267	1			T6	1		T148	7		T149	16
minimum	14573	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T146	1		T135	20		T138	25
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T9	1		T19	1		T136	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1722	1			T13	2		T17	1		T20	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	1		T41	1		T135	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	2		T15	1		T137	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	6		T133	18		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T18	10		T50	12		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T131	9		T162	1		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	10		T230	1		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	1		T43	5		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T188	1		T267	9		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T44	4		T149	9		T233	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	2		T49	1		T139	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T19	1		T144	17		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T143	1		T150	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T25	2		T137	17		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	2		T50	14		T136	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	5		T50	12		T134	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T6	1		T148	2		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T149	16		T268	14		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14462	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T146	6		T244	2		T159	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T136	20		T45	1		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T17	9		T85	7		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	5		T41	1		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	8		T161	1		T172	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	7		T133	18		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T18	4		T50	8		T184	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T131	16		T162	15		T253	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	7		T134	10		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	1		T162	2		T184	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T214	7		T256	4		T245	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T44	1		T271	11		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T49	2		T234	11		T27	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	14		T164	11		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	12		T161	1		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T145	13		T185	7		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T50	13		T136	4		T151	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	2		T50	6		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T148	5		T240	5		T272	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T268	15		T199	15		T273	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	1		T43	2		T44	1