Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20092

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3858

1

T40

2

T24

2

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17563

1

T3

19

T4

20

T5

8

auto[1]

6387

1

T5

7

T9

1

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T25	2		T298	1		T338	1
values[0]	96	1			T134	25		T236	29		T297	11
values[1]	688	1			T24	2		T50	20		T45	7
values[2]	726	1			T18	14		T137	17		T147	3
values[3]	707	1			T41	2		T48	13		T49	3
values[4]	3143	1			T13	2		T15	9		T17	10
values[5]	496	1			T40	2		T50	18		T135	4
values[6]	769	1			T16	2		T19	1		T244	3
values[7]	813	1			T48	17		T229	27		T136	40
values[8]	894	1			T6	1		T230	1		T135	9
values[9]	1052	1			T5	7		T9	1		T14	6
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	893	1			T24	2		T50	20		T134	25
values[1]	715	1			T18	14		T48	13		T135	16
values[2]	787	1			T49	3		T146	7		T136	12
values[3]	3081	1			T13	2		T15	9		T17	10
values[4]	547	1			T40	2		T50	18		T183	11
values[5]	833	1			T16	2		T19	1		T229	27
values[6]	815	1			T48	17		T136	21		T138	15
values[7]	707	1			T6	1		T14	6		T50	27
values[8]	812	1			T5	7		T9	1		T19	1
values[9]	183	1			T280	14		T344	22		T291	1
minimum	14577	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T147	1		T144	17		T46	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T24	2		T50	12		T134	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	10		T48	6		T173	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T135	16		T137	17		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T146	1		T266	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T49	1		T136	8		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T13	2		T15	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T19	1		T41	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	12		T151	1		T271	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	2		T183	11		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T16	2		T19	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T229	13		T136	9		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T136	11		T164	8		T152	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T48	10		T138	15		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	1		T14	1		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T230	1		T135	9		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	5		T9	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T19	1		T25	2		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T280	1		T293	2		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T344	12		T291	1		T292	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14462	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T194	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T147	2		T173	4		T236	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T50	8		T134	9		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	4		T48	7		T173	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T239	16		T236	21		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	6		T162	4		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	2		T136	4		T145	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T15	8		T17	9		T85	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	1		T185	7		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T50	6		T151	11		T271	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T184	2		T159	3		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T162	2		T184	5		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T229	14		T136	10		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T136	10		T164	2		T152	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T48	7		T162	15		T159	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	5		T50	13		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T237	1		T239	12		T238	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	2		T131	16		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	1		T147	10		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T280	13		T293	1		T279	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T344	10		T292	10		T191	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T194	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T298	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T25	2		T338	1		T345	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T236	18		T328	9		T346	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T134	16		T297	6		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T232	10		T173	1		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T24	2		T50	12		T45	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T18	10		T147	1		T144	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T137	17		T139	1		T235	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	6		T146	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T41	1		T49	1		T135	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1735	1			T13	2		T15	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T19	1		T136	8		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T50	12		T135	4		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	2		T183	11		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	2		T19	1		T267	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T244	1		T163	1		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	11		T162	1		T184	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	10		T229	13		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T147	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T230	1		T135	9		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	5		T9	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T19	1		T44	4		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T236	11		T328	6		T346	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T134	9		T297	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T173	4		T292	14		T329	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T50	8		T45	1		T165	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	4		T147	2		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T27	1		T320	6		T236	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	7		T146	6		T162	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T41	1		T49	2		T145	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T15	8		T17	9		T85	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	4		T185	7		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T50	6		T253	14		T301	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T184	2		T159	3		T150	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T271	11		T254	6		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T244	2		T231	19		T172	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	10		T162	2		T184	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	7		T229	14		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T218	6		T164	2		T152	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T237	1		T239	12		T238	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	2		T14	5		T50	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	1		T147	10		T132	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T147	3		T144	1		T46	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T24	2		T50	9		T134	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T18	5		T48	8		T173	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T135	1		T137	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T146	7		T266	1		T162	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	3		T136	5		T145	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T13	2		T15	9		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	1		T41	2		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T50	7		T151	12		T271	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	2		T183	1		T184	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	2		T19	1		T162	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T229	15		T136	11		T244	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T136	11		T164	3		T152	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T48	8		T138	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T14	6		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T230	1		T135	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	5		T9	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	1		T25	2		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T280	14		T293	2		T279	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T344	11		T291	1		T292	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14556	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T194	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T144	16		T232	9		T236	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T50	11		T134	15		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T18	9		T48	5		T287	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T135	15		T137	16		T235	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T133	17		T186	11		T234	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T136	7		T259	15		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T20	11		T43	1		T130	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T185	12		T243	8		T274	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T50	11		T271	9		T302	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T183	10		T242	10		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T184	13		T164	5		T197	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T229	12		T136	8		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	10		T164	7		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	9		T138	14		T159	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T50	13		T233	15		T190	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	8		T137	14		T149	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	2		T131	8		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T44	1		T132	15		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T293	1		T303	8		T347	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T344	11		T292	13		T191	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T194	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T298	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T25	2		T338	1		T345	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T236	12		T328	7		T346	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T134	10		T297	6		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T232	1		T173	5		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T24	2		T50	9		T45	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T18	5		T147	3		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	1		T139	1		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	8		T146	7		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T41	2		T49	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T13	2		T15	9		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T19	1		T136	5		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T50	7		T135	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	2		T183	1		T184	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	2		T19	1		T267	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T244	3		T163	1		T231	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T136	11		T162	3		T184	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	8		T229	15		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T6	1		T147	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T230	1		T135	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T5	5		T9	1		T14	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T19	1		T44	4		T147	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T345	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T236	17		T328	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T134	15		T297	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T232	9		T292	2		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T50	11		T45	1		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	9		T144	16		T133	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T137	16		T235	18		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	5		T234	12		T152	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T135	15		T158	14		T132	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T20	11		T43	1		T130	42
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T136	7		T259	15		T185	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T50	11		T135	3		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T183	10		T242	10		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T267	8		T271	9		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T231	12		T172	21		T305	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T136	10		T184	13		T164	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	9		T229	12		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T164	7		T152	9		T190	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T135	8		T137	14		T149	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	2		T50	13		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T44	1		T132	15		T148	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11