Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19966

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3984

1

T5

7

T40

2

T18

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17524

1

T3

19

T4

20

T5

8

auto[1]

6426

1

T5

7

T9

1

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	607	1			T5	7		T6	1		T24	1
values[0]	5	1			T250	3		T348	1		T265	1
values[1]	769	1			T9	1		T19	1		T146	7
values[2]	3024	1			T13	2		T14	6		T17	10
values[3]	553	1			T40	2		T41	2		T135	9
values[4]	854	1			T15	9		T18	14		T48	13
values[5]	749	1			T19	1		T48	17		T50	20
values[6]	771	1			T230	1		T44	5		T144	6
values[7]	697	1			T24	2		T19	1		T49	3
values[8]	671	1			T25	2		T137	17		T139	1
values[9]	962	1			T16	2		T50	45		T136	12
minimum	14288	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T9	1		T146	7		T135	20
values[1]	2979	1			T13	2		T14	6		T17	10
values[2]	589	1			T40	2		T15	9		T48	13
values[3]	893	1			T18	14		T50	20		T131	25
values[4]	656	1			T19	1		T48	17		T43	6
values[5]	734	1			T44	5		T144	17		T186	26
values[6]	717	1			T24	2		T19	1		T49	3
values[7]	667	1			T16	2		T25	2		T137	17
values[8]	943	1			T5	7		T50	45		T134	25
values[9]	208	1			T6	1		T268	29		T269	1
minimum	14824	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T146	1		T135	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	6		T138	10		T235	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T13	2		T14	1		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T41	1		T147	1		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	1		T48	6		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	2		T135	9		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T50	12		T46	1		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T18	10		T131	9		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T19	1		T48	10		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T43	5		T229	13		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T144	17		T186	12		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	4		T233	16		T271	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	2		T49	1		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	1		T139	1		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	2		T150	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T25	2		T137	17		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	8		T147	1		T300	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T5	5		T50	26		T134	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T6	1		T269	1		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T268	14		T278	6		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14553	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T19	1		T132	16		T152	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	6		T136	10		T159	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	1		T244	2		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T14	5		T17	9		T85	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	1		T147	2		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	8		T48	7		T161	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T164	4		T342	10		T294	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T50	8		T184	2		T253	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T18	4		T131	16		T162	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	7		T134	10		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	1		T229	14		T162	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T186	14		T214	7		T256	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T44	1		T271	11		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	2		T234	11		T173	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T159	14		T27	1		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T150	12		T161	1		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T145	13		T185	7		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	4		T151	13		T175	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	2		T50	19		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T240	5		T272	15		T349	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T268	15		T199	15		T273	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T132	9		T152	10		T250	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T6	1		T24	1		T51	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T5	5		T134	16		T158	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T348	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T250	1		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T146	1		T135	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T19	1		T45	6		T138	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T13	2		T14	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T26	2		T183	11		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T149	14		T161	1		T172	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T40	2		T41	1		T135	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T15	1		T48	6		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T18	10		T162	1		T161	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	1		T48	10		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T43	5		T229	13		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T230	1		T259	16		T186	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	4		T144	6		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T24	2		T49	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T19	1		T139	1		T159	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T139	1		T150	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T25	2		T137	17		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	2		T136	8		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T50	26		T158	15		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14194	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T241	5		T350	15		T240	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T5	2		T134	9		T320	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T250	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T146	6		T136	20		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T45	1		T244	2		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T14	5		T17	9		T85	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	12		T236	12		T165	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T161	1		T172	17		T310	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	1		T147	2		T133	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	8		T48	7		T184	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	4		T162	15		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	7		T50	8		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	1		T229	14		T131	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T186	14		T239	12		T214	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	1		T258	14		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	2		T234	11		T249	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T159	14		T27	1		T218	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T150	12		T161	1		T173	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T185	7		T148	8		T295	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	4		T151	13		T236	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T50	19		T145	13		T132	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	1		T146	7		T135	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	6		T138	1		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T13	2		T14	6		T17	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	2		T147	3		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	9		T48	8		T161	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T40	2		T135	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T50	9		T46	1		T184	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T18	5		T131	17		T162	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	1		T48	8		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T43	5		T229	15		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T144	1		T186	15		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T44	4		T233	1		T271	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T24	2		T49	3		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	1		T139	1		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	2		T150	13		T161	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T25	2		T137	1		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	5		T147	1		T300	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T5	5		T50	21		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T6	1		T269	1		T240	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T268	16		T278	1		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14662	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T19	1		T132	10		T152	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T135	18		T136	8		T138	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	1		T138	9		T235	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T20	11		T130	42		T261	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T183	10		T133	17		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	5		T172	21		T351	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T135	8		T137	14		T164	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T50	11		T233	19		T152	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	9		T131	8		T161	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T48	9		T134	10		T259	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	1		T229	12		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T144	16		T186	11		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T44	1		T233	15		T271	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T234	12		T274	14		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T159	14		T164	6		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T236	7		T276	1		T352	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T137	16		T185	12		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	7		T232	8		T175	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T5	2		T50	24		T134	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T272	8		T349	3		T353	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T268	13		T278	5		T199	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T136	10		T318	8		T95	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T132	15		T152	11		T278	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T6	1		T24	1		T51	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	5		T134	10		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T348	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T250	3		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T146	7		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	1		T45	6		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T13	2		T14	6		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T26	2		T183	1		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T149	1		T161	2		T172	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	2		T41	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	9		T48	8		T184	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T18	5		T162	16		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T19	1		T48	8		T50	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T43	5		T229	15		T131	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T230	1		T259	1		T186	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T44	4		T144	1		T258	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T24	2		T49	3		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	1		T139	1		T159	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T139	1		T150	13		T161	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T25	2		T137	1		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	2		T136	5		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T50	21		T158	1		T145	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14288	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T241	5		T277	15		T354	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	2		T134	15		T158	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T135	15		T136	18		T138	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T45	1		T138	9		T235	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T20	11		T130	42		T261	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T183	10		T152	12		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T149	13		T172	21		T190	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	8		T137	14		T133	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T48	5		T233	19		T152	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	9		T161	14		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T48	9		T50	11		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	1		T229	12		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T259	15		T186	11		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	1		T144	5		T233	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T144	16		T234	12		T267	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T159	14		T164	6		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T276	1		T246	7		T352	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T137	16		T185	12		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	7		T232	8		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T50	24		T158	14		T132	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11