Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20161

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3789

1

T5

7

T40

2

T24

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17978

1

T3

19

T4

20

T5

15

auto[1]

5972

1

T9

1

T40

2

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	277	1			T9	1		T41	2		T136	19
values[0]	33	1			T184	1		T163	1		T332	28
values[1]	791	1			T5	7		T14	6		T48	13
values[2]	937	1			T15	9		T18	14		T230	1
values[3]	665	1			T136	12		T137	15		T147	11
values[4]	714	1			T25	2		T135	16		T147	3
values[5]	573	1			T16	2		T146	7		T136	21
values[6]	780	1			T19	1		T48	17		T49	3
values[7]	618	1			T24	2		T19	1		T50	18
values[8]	3098	1			T13	2		T17	10		T20	12
values[9]	910	1			T6	1		T40	2		T19	1
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	935	1			T5	7		T14	6		T15	9
values[1]	829	1			T230	1		T44	5		T147	11
values[2]	536	1			T136	12		T137	15		T147	3
values[3]	860	1			T16	2		T146	7		T25	2
values[4]	574	1			T134	21		T135	4		T139	1
values[5]	763	1			T19	2		T48	17		T49	3
values[6]	2927	1			T13	2		T24	2		T17	10
values[7]	736	1			T50	20		T135	9		T138	15
values[8]	966	1			T6	1		T9	1		T40	2
values[9]	72	1			T138	10		T143	1		T175	24
minimum	14752	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T14	1		T18	10		T48	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	5		T15	1		T229	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T230	1		T44	4		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T147	1		T260	13		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T136	8		T137	15		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T131	9		T148	2		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T146	1		T135	16		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T16	2		T25	2		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T135	4		T139	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T134	11		T46	1		T148	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T48	10		T49	1		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	2		T143	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T13	2		T17	1		T20	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	2		T149	16		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T135	9		T143	1		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T50	12		T138	15		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	1		T9	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T40	2		T136	9		T137	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T355	1		T356	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T138	10		T143	1		T175	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14509	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T184	1		T163	1		T239	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	5		T18	4		T48	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	2		T15	8		T229	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	1		T173	4		T271	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T147	10		T249	10		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T136	4		T147	2		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	16		T148	5		T159	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T146	6		T133	18		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T136	10		T45	1		T159	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T150	5		T161	1		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T134	10		T148	8		T159	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T48	7		T49	2		T50	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T184	2		T253	14		T239	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T17	9		T85	7		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T151	11		T275	10		T310	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T258	14		T197	12		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T50	8		T242	17		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	1		T50	13		T132	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	10		T244	2		T162	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T175	13		T357	14		T358	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T239	12		T252	10		T332	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T9	1		T41	1		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T136	9		T138	10		T243	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T333	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T184	1		T163	1		T332	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	1		T48	6		T43	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	5		T229	13		T234	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T18	10		T230	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T15	1		T260	13		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T136	8		T137	15		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T147	1		T131	9		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T135	16		T147	1		T158	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T25	2		T158	13		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T146	1		T139	1		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	2		T136	11		T45	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T48	10		T49	1		T135	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	1		T134	11		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T50	12		T134	16		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T24	2		T19	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T13	2		T17	1		T20	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T50	12		T144	17		T161	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T6	1		T19	1		T50	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T40	2		T137	17		T138	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T41	1		T320	6		T359	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T136	10		T243	9		T175	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T332	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	5		T48	7		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	2		T229	14		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T18	4		T44	1		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	8		T249	10		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	4		T164	2		T239	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	10		T131	16		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T147	2		T133	18		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T159	3		T238	15		T271	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T146	6		T150	5		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	10		T45	1		T148	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	7		T49	2		T162	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T134	10		T184	2		T253	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T50	6		T134	9		T145	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T310	13		T283	10		T292	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T17	9		T85	7		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T50	8		T151	11		T242	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T50	13		T132	11		T184	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T244	2		T162	15		T173	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	6		T18	5		T48	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	5		T15	9		T229	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T230	1		T44	4		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T147	11		T260	1		T249	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	5		T137	1		T147	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T131	17		T148	6		T159	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T146	7		T135	1		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T16	2		T25	2		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	1		T139	1		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	11		T46	1		T148	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	8		T49	3		T50	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T19	2		T143	1		T184	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T13	2		T17	10		T20	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T24	2		T149	1		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	1		T143	1		T258	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	9		T138	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	1		T9	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T40	2		T136	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T355	1		T356	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T138	1		T143	1		T175	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14598	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T184	1		T163	1		T239	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T18	9		T48	5		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	2		T229	12		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T44	1		T235	18		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T260	12		T236	17		T287	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	7		T137	14		T158	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T131	8		T148	1		T218	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T135	15		T144	5		T133	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T136	10		T45	1		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T135	3		T164	5		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T134	10		T148	10		T159	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	9		T50	11		T259	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T239	13		T214	8		T294	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T20	11		T130	42		T261	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T149	15		T308	4		T275	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T135	8		T233	9		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	11		T138	14		T144	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	13		T132	9		T184	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T136	8		T137	16		T243	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T138	9		T175	10		T358	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T241	14		T360	9		T195	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T239	10		T332	12		T247	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T9	1		T41	2		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T136	11		T138	1		T243	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T333	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T184	1		T163	1		T332	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	6		T48	8		T43	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	5		T229	15		T234	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T18	5		T230	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	9		T260	1		T249	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T136	5		T137	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T147	11		T131	17		T148	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T135	1		T147	3		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T25	2		T158	1		T159	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T146	7		T139	1		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T16	2		T136	11		T45	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	8		T49	3		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T19	1		T134	11		T184	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T50	7		T134	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	2		T19	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T13	2		T17	10		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	9		T144	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T19	1		T50	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T40	2		T137	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T320	7		T359	6		T247	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T136	8		T138	9		T243	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T333	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T332	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T48	5		T43	1		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	2		T229	12		T234	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T18	9		T44	1		T235	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T260	12		T236	17		T287	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	7		T137	14		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T131	8		T148	1		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T135	15		T158	14		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T158	12		T274	14		T238	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T238	4		T241	17		T195	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	10		T45	1		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T48	9		T135	3		T259	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T134	10		T239	13		T214	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	11		T134	15		T132	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T149	15		T308	4		T310	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T20	11		T130	42		T261	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	11		T144	16		T161	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T50	13		T132	9		T184	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T137	16		T138	14		T267	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11