Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20098

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3852

1

T16

2

T48

13

T50

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17877

1

T3

19

T4

20

T5

15

auto[1]

6073

1

T6

1

T9

1

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	223	1			T163	1		T218	11		T151	1
values[0]	47	1			T19	1		T190	22		T295	8
values[1]	646	1			T40	2		T24	2		T19	1
values[2]	3154	1			T13	2		T17	10		T20	12
values[3]	985	1			T5	7		T9	1		T43	6
values[4]	764	1			T14	6		T134	21		T147	3
values[5]	648	1			T19	1		T135	4		T136	19
values[6]	495	1			T18	14		T48	17		T146	7
values[7]	609	1			T15	9		T16	2		T25	2
values[8]	826	1			T41	2		T49	3		T44	5
values[9]	999	1			T6	1		T50	18		T139	1
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	774	1			T40	2		T24	2		T19	1
values[1]	3106	1			T13	2		T17	10		T20	12
values[2]	988	1			T5	7		T9	1		T43	6
values[3]	671	1			T14	6		T134	21		T147	11
values[4]	701	1			T19	1		T48	17		T135	20
values[5]	504	1			T15	9		T18	14		T146	7
values[6]	614	1			T16	2		T49	3		T25	2
values[7]	851	1			T41	2		T44	5		T136	12
values[8]	928	1			T6	1		T50	18		T158	15
values[9]	82	1			T151	12		T252	11		T329	31
minimum	14731	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	2		T24	2		T19	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T48	6		T229	13		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T13	2		T17	1		T20	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T230	1		T46	1		T164	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T5	5		T9	1		T137	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T43	5		T135	9		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	1		T235	19		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	11		T147	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T19	1		T48	10		T135	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	16		T159	1		T149	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	1		T18	10		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T146	1		T134	16		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	1		T25	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	2		T139	1		T148	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	1		T44	4		T136	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T144	17		T163	1		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	1		T143	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T50	12		T158	15		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T361	1		T362	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T151	1		T252	1		T329	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14516	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T238	5		T295	1		T257	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T363	9		T322	14		T364	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T48	7		T229	14		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T17	9		T85	7		T50	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T164	4		T239	12		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	2		T147	2		T162	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	1		T45	1		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	5		T132	11		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T134	10		T147	10		T161	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	7		T136	10		T301	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T159	4		T161	1		T165	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T15	8		T18	4		T162	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T146	6		T134	9		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	2		T184	5		T133	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T148	5		T243	9		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T41	1		T44	1		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T218	6		T271	11		T236	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T145	13		T162	4		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T50	6		T150	17		T231	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T362	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T151	11		T252	10		T329	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T238	4		T295	7		T257	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T237	4		T245	1		T283	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T163	1		T218	11		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T19	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T190	22		T295	1		T353	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T40	2		T24	2		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	6		T138	10		T238	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T13	2		T17	1		T20	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T230	1		T229	13		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T5	5		T9	1		T137	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T43	5		T135	9		T45	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	1		T147	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T134	11		T143	1		T186	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	1		T135	4		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T147	1		T159	1		T149	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T18	10		T48	10		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T146	1		T135	16		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T25	2		T133	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	2		T134	16		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T41	1		T49	1		T44	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T144	17		T163	1		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	1		T139	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T50	12		T158	15		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T237	1		T245	9		T283	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T329	14		T328	11		T365	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T295	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T173	10		T363	9		T322	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	7		T238	4		T252	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T17	9		T85	7		T50	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T229	14		T136	10		T131	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	2		T159	14		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	1		T45	1		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	5		T147	2		T162	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T134	10		T186	14		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	10		T301	15		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T147	10		T159	4		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T18	4		T48	7		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T146	6		T238	9		T276	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	8		T133	18		T258	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	9		T244	2		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T41	1		T49	2		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T218	6		T231	12		T197	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T145	13		T162	4		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T50	6		T150	17		T151	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	2		T24	2		T19	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	8		T229	15		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T13	2		T17	10		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T230	1		T46	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	5		T9	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T43	5		T135	1		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	6		T235	1		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	11		T147	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	1		T48	8		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	1		T159	5		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T15	9		T18	5		T162	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T146	7		T134	10		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	3		T25	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	2		T139	1		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T41	2		T44	4		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T144	1		T163	1		T218	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	1		T143	1		T145	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T50	7		T158	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T361	1		T362	10		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T151	12		T252	11		T329	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14593	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T238	5		T295	8		T257	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T137	14		T183	10		T260	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	5		T229	12		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T20	11		T50	24		T130	42
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T164	5		T233	15		T239	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T5	2		T137	16		T138	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T43	1		T135	8		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T235	18		T132	9		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	10		T366	7		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	9		T135	3		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	15		T149	15		T165	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T18	9		T242	7		T267	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T134	15		T164	7		T267	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T184	13		T133	17		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T148	1		T243	8		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	1		T136	7		T185	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T144	16		T271	9		T236	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T132	15		T237	1		T233	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T50	11		T158	14		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T329	16		T367	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T158	12		T368	2		T369	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T238	4		T257	8		T275	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T237	4		T245	10		T283	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T163	1		T218	1		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T19	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T190	1		T295	8		T353	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	2		T24	2		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	8		T138	1		T238	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T13	2		T17	10		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T230	1		T229	15		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	5		T9	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T43	5		T135	1		T45	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	6		T147	3		T162	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T134	11		T143	1		T186	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T19	1		T135	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	11		T159	5		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T18	5		T48	8		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	7		T135	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	9		T25	2		T133	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	2		T134	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	2		T49	3		T44	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T144	1		T163	1		T218	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	1		T139	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T50	7		T158	1		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T237	1		T283	5		T332	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T218	10		T329	16		T339	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T190	21		T353	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T158	12		T260	12		T368	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	5		T138	9		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T20	11		T50	24		T130	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T229	12		T136	10		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	2		T137	16		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T43	1		T135	8		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T132	9		T148	10		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T134	10		T186	11		T234	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T135	3		T136	8		T235	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T149	15		T165	14		T342	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T18	9		T48	9		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T135	15		T238	11		T276	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T133	17		T152	11		T271	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	15		T148	1		T243	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T44	1		T136	7		T184	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T144	16		T231	12		T197	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T132	15		T185	12		T233	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	11		T158	14		T231	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11