Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20088

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3862

1

T16

2

T48

13

T50

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17874

1

T3

19

T4

20

T5

15

auto[1]

6076

1

T6

1

T9

1

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T245	10		T269	1		T240	6
values[0]	99	1			T19	1		T173	11		T190	22
values[1]	637	1			T40	2		T24	2		T19	1
values[2]	3035	1			T13	2		T17	10		T20	12
values[3]	995	1			T5	7		T9	1		T50	27
values[4]	807	1			T14	6		T134	21		T147	3
values[5]	650	1			T19	1		T135	4		T136	19
values[6]	523	1			T48	17		T146	7		T25	2
values[7]	618	1			T15	9		T16	2		T18	14
values[8]	781	1			T41	2		T49	3		T44	5
values[9]	1224	1			T6	1		T50	18		T139	1
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	974	1			T40	2		T24	2		T19	2
values[1]	3080	1			T13	2		T17	10		T20	12
values[2]	917	1			T5	7		T9	1		T43	6
values[3]	715	1			T14	6		T134	21		T147	11
values[4]	661	1			T19	1		T48	17		T135	20
values[5]	510	1			T15	9		T18	14		T146	7
values[6]	718	1			T16	2		T49	3		T25	2
values[7]	764	1			T41	2		T44	5		T136	12
values[8]	846	1			T6	1		T50	18		T158	15
values[9]	184	1			T163	1		T151	12		T231	32
minimum	14581	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T40	2		T24	2		T19	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T48	6		T229	13		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T13	2		T17	1		T20	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T230	1		T46	1		T299	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T5	5		T9	1		T137	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T43	5		T135	9		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T235	19		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T134	11		T147	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	1		T48	10		T135	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T135	16		T159	1		T149	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	1		T18	10		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T146	1		T134	16		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	1		T25	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T16	2		T139	1		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	1		T44	4		T136	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T144	17		T163	1		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	1		T143	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T50	12		T158	15		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T316	1		T240	1		T222	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T163	1		T151	1		T231	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14469	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T257	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T184	2		T173	10		T363	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T48	7		T229	14		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T17	9		T85	7		T50	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T239	12		T249	10		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	2		T147	2		T162	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	1		T45	1		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	5		T132	11		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	10		T147	10		T161	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	7		T301	15		T295	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T159	4		T161	1		T165	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T15	8		T18	4		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T146	6		T134	9		T164	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	2		T184	5		T133	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T244	2		T148	5		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	1		T44	1		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T218	6		T271	11		T236	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T145	13		T162	4		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	6		T150	17		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T316	3		T240	5		T222	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T151	11		T231	19		T252	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T257	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T245	1		T240	1		T178	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T19	1		T173	1		T182	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T190	22		T370	2		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T40	2		T24	2		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	6		T138	10		T164	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1681	1			T13	2		T17	1		T20	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T230	1		T229	13		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	5		T9	1		T50	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T43	5		T135	9		T45	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	1		T147	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T134	11		T143	1		T186	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	1		T135	4		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T147	1		T159	1		T149	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T48	10		T25	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T146	1		T135	16		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	1		T18	10		T133	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	2		T134	16		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	1		T49	1		T44	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T144	17		T163	1		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T6	1		T139	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T50	12		T158	15		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T245	9		T240	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T173	10		T182	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T295	7		T310	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T363	9		T322	14		T310	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	7		T164	4		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T17	9		T85	7		T50	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T229	14		T136	10		T131	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	2		T50	13		T159	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T43	1		T45	1		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	5		T147	2		T162	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T134	10		T186	14		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	10		T152	12		T301	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	10		T159	4		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T48	7		T162	2		T295	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T146	6		T243	9		T238	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	8		T18	4		T133	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T134	9		T244	2		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T41	1		T49	2		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T218	6		T231	12		T197	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T145	13		T162	4		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T50	6		T150	17		T151	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	2		T24	2		T19	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T48	8		T229	15		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T13	2		T17	10		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T230	1		T46	1		T299	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	5		T9	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	5		T135	1		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	6		T235	1		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T134	11		T147	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	1		T48	8		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T135	1		T159	5		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	9		T18	5		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	7		T134	10		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T49	3		T25	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T16	2		T139	1		T244	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T41	2		T44	4		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T144	1		T163	1		T218	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T6	1		T143	1		T145	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T50	7		T158	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T316	4		T240	6		T222	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T163	1		T151	12		T231	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14555	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T257	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T137	14		T158	12		T183	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T48	5		T229	12		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T20	11		T50	24		T130	42
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T233	15		T239	12		T236	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	2		T137	16		T138	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T43	1		T135	8		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T235	18		T132	9		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	10		T366	7		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	9		T135	3		T259	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	15		T149	15		T165	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T18	9		T136	8		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T134	15		T164	7		T267	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T184	13		T133	17		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T148	1		T243	8		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	1		T136	7		T185	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T144	16		T271	9		T236	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T132	15		T237	1		T233	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	11		T158	14		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T222	11		T332	12		T334	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T231	12		T262	12		T278	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T333	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T257	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T245	10		T240	6		T178	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T19	1		T173	11		T182	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T190	1		T370	2		T295	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	2		T24	2		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	8		T138	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T13	2		T17	10		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T230	1		T229	15		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	5		T9	1		T50	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T43	5		T135	1		T45	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	6		T147	3		T162	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T134	11		T143	1		T186	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	1		T135	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T147	11		T159	5		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	8		T25	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T146	7		T135	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	9		T18	5		T133	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	2		T134	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T41	2		T49	3		T44	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T144	1		T163	1		T218	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T6	1		T139	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T50	7		T158	1		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T178	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T182	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T190	21		T310	11		T353	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T158	12		T183	10		T260	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	5		T138	9		T164	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T20	11		T50	11		T130	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T229	12		T136	10		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	2		T50	13		T137	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T43	1		T135	8		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T259	15		T132	9		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T134	10		T186	11		T234	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T135	3		T136	8		T235	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T149	15		T239	10		T165	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T48	9		T267	8		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	15		T243	8		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T18	9		T133	17		T242	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T134	15		T148	1		T164	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	1		T136	7		T184	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T144	16		T231	12		T197	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T132	15		T185	12		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T50	11		T158	14		T218	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11