Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20433

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3517

1

T9

1

T40

2

T14

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17778

1

T3

19

T4

20

T5

15

auto[1]

6172

1

T40

2

T13

2

T24

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T151	14		T257	18		-	-
values[0]	49	1			T295	8		T92	1		T328	15
values[1]	832	1			T18	14		T230	1		T138	15
values[2]	708	1			T16	2		T48	30		T158	13
values[3]	653	1			T41	2		T134	25		T229	27
values[4]	766	1			T5	7		T135	9		T44	5
values[5]	3008	1			T13	2		T17	10		T20	12
values[6]	656	1			T19	1		T49	3		T25	2
values[7]	729	1			T9	1		T40	2		T14	6
values[8]	759	1			T50	20		T136	12		T139	1
values[9]	1204	1			T6	1		T24	2		T15	9
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1002	1			T18	14		T230	1		T139	1
values[1]	671	1			T16	2		T48	30		T45	7
values[2]	781	1			T5	7		T41	2		T134	25
values[3]	3087	1			T13	2		T17	10		T20	12
values[4]	618	1			T19	1		T50	27		T137	17
values[5]	622	1			T9	1		T40	2		T49	3
values[6]	751	1			T14	6		T19	1		T146	7
values[7]	752	1			T6	1		T136	12		T137	15
values[8]	857	1			T24	2		T15	9		T50	20
values[9]	213	1			T19	1		T231	25		T344	22
minimum	14596	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T18	10		T230	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T158	13		T300	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	2		T138	15		T144	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T48	16		T45	6		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	5		T41	1		T134	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	9		T131	9		T183	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1711	1			T13	2		T17	1		T20	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T135	16		T44	4		T158	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T19	1		T50	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T137	17		T26	2		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	1		T135	4		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	1		T40	2		T43	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T19	1		T146	1		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T134	11		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	1		T136	8		T137	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T145	1		T259	16		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T24	2		T159	15		T149	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T15	1		T50	12		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T231	13		T344	12		T241	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T19	1		T319	1		T342	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14470	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T218	1		T152	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T18	4		T159	3		T150	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T162	15		T234	11		T239	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T132	11		T27	1		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	14		T45	1		T186	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	2		T41	1		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T136	10		T131	16		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T17	9		T85	7		T50	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T44	1		T184	5		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	13		T147	2		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T162	2		T95	14		T329	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T49	2		T249	10		T305	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T43	1		T231	19		T172	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T146	6		T197	12		T301	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	5		T134	10		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T136	4		T161	1		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T145	13		T148	5		T258	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T159	14		T150	5		T151	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	8		T50	8		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T231	12		T344	10		T241	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T342	10		T371	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T218	6		T152	12		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T151	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T257	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T328	9		T179	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T295	1		T92	1		T182	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	10		T230	1		T138	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T300	1		T143	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	2		T267	9		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	16		T158	13		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	1		T134	16		T229	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T45	6		T131	9		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	5		T135	9		T235	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T44	4		T136	9		T158	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1713	1			T13	2		T17	1		T20	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	16		T26	2		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	1		T49	1		T135	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T25	2		T137	17		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T19	1		T146	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	1		T40	2		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T136	8		T139	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T50	12		T266	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T6	1		T24	2		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T15	1		T19	1		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T151	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T257	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T328	6		T179	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T295	7		T182	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T18	4		T159	3		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T218	6		T152	12		T239	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T173	13		T254	6		T318	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T48	14		T162	15		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	1		T134	9		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	1		T131	16		T148	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	2		T244	2		T161	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T44	1		T136	10		T320	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T17	9		T85	7		T50	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T162	2		T184	5		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	2		T242	7		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T172	17		T280	13		T268	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T146	6		T305	13		T256	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	5		T43	1		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	4		T197	12		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T50	8		T159	4		T258	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T159	14		T150	5		T161	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T15	8		T136	10		T145	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T18	5		T230	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T158	1		T300	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	2		T138	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	16		T45	6		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T5	5		T41	2		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T136	11		T131	17		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T13	2		T17	10		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T135	1		T44	4		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T19	1		T50	14		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T137	1		T26	2		T162	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	3		T135	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T40	2		T43	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T19	1		T146	7		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	6		T134	11		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T136	5		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T145	14		T259	1		T148	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T24	2		T159	15		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	9		T50	9		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T231	13		T344	11		T241	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T19	1		T319	1		T342	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14555	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T218	7		T152	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	9		T149	13		T152	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T158	12		T234	12		T149	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T138	14		T144	5		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	14		T45	1		T186	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	2		T134	15		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	8		T131	8		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T20	11		T50	11		T130	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T135	15		T44	1		T158	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T50	13		T144	16		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T137	16		T95	16		T359	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	3		T305	13		T308	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	1		T138	9		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T197	11		T302	7		T256	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T134	10		T185	12		T236	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T136	7		T137	14		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T259	15		T148	1		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T159	14		T149	15		T233	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	11		T136	10		T132	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T231	12		T344	11		T241	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T342	26		T371	4		T354	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T176	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T151	14		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T257	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T328	7		T179	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T295	8		T92	1		T182	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T18	5		T230	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T300	1		T143	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	2		T267	1		T173	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T48	16		T158	1		T162	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T41	2		T134	10		T229	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	6		T131	17		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	5		T135	1		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	4		T136	11		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T13	2		T17	10		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	1		T26	2		T162	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T19	1		T49	3		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T25	2		T137	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T19	1		T146	7		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T40	2		T14	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T136	5		T139	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	9		T266	1		T159	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	1		T24	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T15	9		T19	1		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T257	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T328	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T182	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	9		T138	14		T149	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T149	8		T152	12		T239	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T267	8		T318	6		T278	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	14		T158	12		T186	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T134	15		T229	12		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T45	1		T131	8		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	2		T135	8		T235	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T44	1		T136	8		T158	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T20	11		T50	24		T130	42
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	15		T184	13		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T135	3		T242	7		T276	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T137	16		T172	21		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T305	13		T302	7		T256	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T43	1		T134	10		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T136	7		T197	11		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	11		T260	12		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T137	14		T159	14		T149	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T136	10		T259	15		T132	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11