Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17802

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

6148

1

T6

1

T9

1

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17489

1

T3

19

T4

20

T5

15

auto[1]

6461

1

T6

1

T13

2

T16

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	274	1			T41	2		T131	25		T150	6
values[0]	115	1			T48	17		T237	5		T152	25
values[1]	607	1			T19	1		T48	13		T134	25
values[2]	887	1			T16	2		T50	20		T229	27
values[3]	536	1			T6	1		T50	27		T147	12
values[4]	803	1			T18	14		T136	21		T138	15
values[5]	689	1			T5	7		T43	6		T139	1
values[6]	680	1			T14	6		T19	1		T230	1
values[7]	643	1			T40	2		T44	5		T147	3
values[8]	891	1			T9	1		T19	1		T146	7
values[9]	3271	1			T13	2		T24	2		T15	9
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	727	1			T19	1		T48	13		T50	20
values[1]	3067	1			T13	2		T16	2		T17	10
values[2]	541	1			T6	1		T18	14		T147	1
values[3]	799	1			T5	7		T136	21		T138	15
values[4]	708	1			T14	6		T19	1		T43	6
values[5]	609	1			T40	2		T230	1		T44	5
values[6]	753	1			T139	1		T143	1		T132	25
values[7]	826	1			T9	1		T19	1		T146	7
values[8]	946	1			T24	2		T15	9		T49	3
values[9]	124	1			T41	2		T234	24		T281	13
minimum	14850	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	6		T137	15		T159	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	1		T50	12		T229	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T218	1		T197	15		T232	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1728	1			T13	2		T16	2		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T18	10		T26	2		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T147	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	5		T138	15		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T136	11		T235	19		T184	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	1		T139	1		T158	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	1		T43	5		T266	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	2		T230	1		T44	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T45	6		T147	1		T144	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T139	1		T143	1		T132	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T159	1		T164	7		T233	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T19	1		T158	13		T149	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	1		T146	1		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T24	2		T49	1		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	1		T136	8		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T41	1		T92	1		T284	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T234	13		T281	1		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14579	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T48	10		T152	23		T281	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	7		T159	14		T150	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T50	8		T229	14		T242	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T218	6		T197	12		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	971	1			T17	9		T85	7		T50	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T18	4		T186	14		T159	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T231	19		T175	6		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	2		T254	6		T276	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T136	10		T184	5		T185	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	13		T151	13		T252	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	5		T43	1		T133	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T44	1		T244	2		T162	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T45	1		T147	2		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T132	9		T148	5		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T159	3		T164	11		T271	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T164	2		T239	12		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T146	6		T134	10		T132	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	2		T50	6		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T15	8		T136	4		T131	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T41	1		T92	12		T284	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T234	11		T281	12		T282	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T43	2		T134	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T48	7		T152	18		T281	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T41	1		T150	1		T161	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T131	9		T322	1		T195	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T237	4		T280	1		T193	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T48	10		T152	13		T372	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	6		T134	16		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T19	1		T135	4		T138	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T159	15		T150	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T16	2		T50	12		T229	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T159	1		T218	11		T164	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T50	14		T147	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T18	10		T138	15		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T136	11		T184	14		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	5		T139	1		T300	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	5		T235	19		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	1		T230	1		T158	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T45	6		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T40	2		T44	4		T132	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T147	1		T184	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T19	1		T139	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	1		T146	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T24	2		T49	1		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1754	1			T13	2		T15	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T41	1		T150	5		T269	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T131	16		T322	14		T195	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T237	1		T280	13		T286	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T48	7		T152	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	7		T134	9		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T242	7		T152	6		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T159	14		T150	12		T218	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	8		T229	14		T184	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T159	4		T164	4		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T50	13		T147	10		T287	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	4		T186	14		T254	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T136	10		T184	5		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	2		T145	13		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	1		T185	7		T172	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T244	2		T162	19		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	5		T45	1		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T44	1		T132	9		T161	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T147	2		T159	3		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T148	5		T239	12		T238	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T146	6		T132	11		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	2		T50	6		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1078	1			T15	8		T17	9		T85	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	8		T137	1		T159	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	1		T50	9		T229	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T218	7		T197	14		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1308	1			T13	2		T16	2		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T18	5		T26	2		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	1		T147	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	5		T138	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T136	11		T235	1		T184	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T19	1		T139	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T14	6		T43	5		T266	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	2		T230	1		T44	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T45	6		T147	3		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T139	1		T143	1		T132	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T159	4		T164	12		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	1		T158	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	1		T146	7		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T24	2		T49	3		T50	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T15	9		T136	5		T131	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T41	2		T92	13		T284	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T234	12		T281	13		T282	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14637	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T48	8		T152	20		T281	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	5		T137	14		T159	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	11		T229	12		T135	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T197	13		T232	2		T165	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1391	1			T20	11		T50	13		T130	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T18	9		T186	11		T218	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T231	12		T260	12		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	2		T138	14		T233	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T136	10		T235	18		T184	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T158	14		T149	13		T176	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	1		T133	17		T172	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T44	1		T243	8		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T45	1		T144	5		T267	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T132	15		T148	1		T238	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T164	6		T233	15		T271	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T158	12		T149	8		T164	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T134	10		T132	9		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T50	11		T135	23		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T136	7		T131	8		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T284	9		T288	4		T373	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T234	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	15		T237	1		T315	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T48	9		T152	21		T281	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T41	2		T150	6		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T131	17		T322	15		T195	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T237	4		T280	14		T193	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T48	8		T152	13		T372	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	8		T134	10		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T19	1		T135	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T159	15		T150	13		T218	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T16	2		T50	9		T229	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T159	5		T218	1		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	1		T50	14		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	5		T138	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T136	11		T184	6		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	5		T139	1		T300	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	5		T235	1		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	1		T230	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	6		T45	6		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	2		T44	4		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T147	3		T184	1		T159	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T19	1		T139	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T9	1		T146	7		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T24	2		T49	3		T50	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1429	1			T13	2		T15	9		T17	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T161	14		T308	4		T269	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T131	8		T195	12		T304	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T237	1		T193	16		T286	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T48	9		T152	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	5		T134	15		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T135	3		T138	9		T144	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T159	14		T197	13		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	11		T229	12		T137	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T218	10		T164	5		T255	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	13		T259	15		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	9		T138	14		T186	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T136	10		T184	13		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	2		T149	13		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T43	1		T235	18		T185	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T158	14		T243	8		T274	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	1		T144	5		T133	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	1		T132	15		T238	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T164	6		T233	15		T239	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T148	1		T149	8		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T132	9		T231	12		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T50	11		T135	23		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1403	1			T20	11		T130	42		T261	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11