Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	1		T24	1		T51	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T241	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T146	1		T135	16		T138	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	1		T19	1		T136	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1711	1			T13	2		T17	1		T20	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	1		T45	6		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	2		T137	15		T149	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	1		T135	9		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T15	1		T18	10		T161	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	6		T162	1		T232	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	10		T50	12		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	1		T43	5		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T230	1		T144	6		T259	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	4		T149	9		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T24	2		T49	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T19	1		T25	2		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T139	2		T27	2		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T137	17		T185	13		T148	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T16	2		T50	14		T136	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T5	5		T50	12		T134	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14194	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T241	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T146	6		T147	10		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T136	20		T132	9		T231	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T17	9		T85	7		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	5		T45	1		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T161	1		T172	17		T238	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T41	1		T133	18		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	8		T18	4		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	7		T162	15		T173	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	7		T50	8		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	1		T131	16		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T186	14		T239	12		T256	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T44	1		T258	14		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	2		T234	11		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T159	14		T164	11		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T27	1		T150	12		T161	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T185	7		T148	8		T173	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	13		T136	4		T148	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T5	2		T50	6		T134	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T146	7		T135	2		T138	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	1		T19	1		T136	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T13	2		T17	10		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	6		T41	2		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	2		T15	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	8		T133	19		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T18	5		T50	9		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T131	17		T162	16		T253	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	8		T230	1		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T19	1		T43	5		T162	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T188	1		T267	1		T28	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T44	4		T149	1		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	2		T49	3		T139	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	1		T144	1		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T143	1		T150	13		T161	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	2		T137	1		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	2		T50	14		T136	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T5	5		T50	7		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T6	1		T148	6		T240	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T149	1		T268	16		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14572	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T135	18		T138	23		T197	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T136	18		T45	1		T235	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T20	11		T130	42		T261	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	8		T183	10		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	14		T149	13		T172	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	5		T133	17		T164	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T18	9		T50	11		T161	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T131	8		T260	12		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	9		T134	10		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	1		T184	13		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T267	8		T28	1		T214	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T44	1		T149	8		T233	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T234	12		T274	14		T275	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	16		T159	14		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T236	7		T276	1		T246	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T137	16		T185	12		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	13		T136	7		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	2		T50	11		T134	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T148	1		T272	8		T277	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T149	15		T268	13		T278	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	1		T24	1		T51	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T241	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T146	7		T135	1		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T19	1		T136	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T13	2		T17	10		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	6		T45	6		T147	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	2		T137	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	2		T135	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T15	9		T18	5		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	8		T162	16		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	8		T50	9		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T19	1		T43	5		T131	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T230	1		T144	1		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T44	4		T149	1		T258	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T24	2		T49	3		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	1		T25	2		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T139	2		T27	3		T150	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	1		T185	8		T148	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T16	2		T50	14		T136	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	440	1			T5	5		T50	7		T134	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14288	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T241	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	15		T138	23		T197	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T136	18		T235	18		T132	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T20	11		T130	42		T261	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T45	1		T237	1		T152	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	14		T149	13		T172	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	8		T183	10		T133	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T18	9		T161	14		T233	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	5		T232	9		T239	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	9		T50	11		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T43	1		T131	8		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T144	5		T259	15		T186	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	1		T149	8		T233	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T234	12		T267	8		T275	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T144	16		T159	14		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T276	1		T246	7		T176	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	16		T185	12		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	13		T136	7		T148	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T5	2		T50	11		T134	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11