Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17820

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

6130

1

T6

1

T9

1

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17398

1

T3

19

T4

20

T5

15

auto[1]

6552

1

T6

1

T13

2

T16

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T279	13		-	-		-	-
values[0]	121	1			T138	10		T152	25		T280	14
values[1]	627	1			T19	1		T48	30		T134	25
values[2]	865	1			T16	2		T50	47		T229	27
values[3]	527	1			T6	1		T147	12		T259	16
values[4]	823	1			T18	14		T136	21		T26	2
values[5]	687	1			T5	7		T43	6		T138	15
values[6]	687	1			T14	6		T19	1		T230	1
values[7]	590	1			T40	2		T44	5		T147	3
values[8]	876	1			T9	1		T146	7		T139	1
values[9]	3580	1			T13	2		T24	2		T15	9
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1012	1			T19	1		T48	30		T50	20
values[1]	3042	1			T13	2		T17	10		T20	12
values[2]	586	1			T6	1		T16	2		T50	27
values[3]	815	1			T5	7		T18	14		T136	21
values[4]	647	1			T19	1		T43	6		T230	1
values[5]	640	1			T40	2		T14	6		T44	5
values[6]	741	1			T139	1		T143	1		T132	25
values[7]	864	1			T19	1		T146	7		T25	2
values[8]	862	1			T9	1		T24	2		T15	9
values[9]	172	1			T41	2		T135	9		T234	24
minimum	14569	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T48	6		T134	16		T137	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T19	1		T48	10		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T218	1		T197	15		T232	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1735	1			T13	2		T17	1		T20	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	2		T143	1		T186	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	1		T16	2		T50	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	5		T18	10		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T136	11		T235	19		T184	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	1		T230	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	5		T266	1		T133	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T40	2		T44	4		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T45	6		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T139	1		T143	1		T132	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T159	1		T27	2		T233	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	1		T158	13		T148	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T146	1		T25	2		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T24	2		T49	1		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	1		T15	1		T134	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T41	1		T135	9		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T234	13		T281	1		T282	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14471	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	7		T134	9		T159	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T48	7		T50	8		T229	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T218	6		T197	12		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	959	1			T17	9		T85	7		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T186	14		T159	4		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	13		T231	19		T175	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	2		T18	4		T254	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T136	10		T184	5		T185	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T145	13		T151	13		T283	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T43	1		T133	18		T172	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T44	1		T244	2		T162	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	5		T45	1		T147	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	9		T161	1		T238	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T159	3		T27	1		T239	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T148	5		T253	14		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	6		T132	11		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	2		T50	6		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T15	8		T134	10		T136	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T41	1		T92	12		T284	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T234	11		T281	12		T282	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	1		T43	2		T44	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T280	1		T222	12		T193	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T138	10		T152	13		T285	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	6		T134	16		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	1		T48	10		T135	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T159	15		T150	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T16	2		T50	26		T229	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T159	1		T218	11		T164	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	1		T147	2		T259	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	10		T26	2		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T136	11		T266	1		T184	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	5		T138	15		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	5		T235	19		T185	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T19	1		T230	1		T158	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	1		T45	6		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	2		T44	4		T132	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T147	1		T144	6		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T139	1		T143	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T9	1		T146	1		T132	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T24	2		T19	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1807	1			T13	2		T15	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T279	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T280	13		T222	3		T286	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	7		T134	9		T237	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T48	7		T184	2		T242	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T159	14		T150	12		T218	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T50	21		T229	14		T239	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T159	4		T164	4		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T147	10		T287	2		T268	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	4		T186	14		T254	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T136	10		T184	5		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	2		T145	13		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	1		T185	7		T133	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T244	2		T162	19		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	5		T45	1		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	1		T132	9		T161	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T147	2		T159	3		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T148	5		T239	12		T238	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	6		T132	11		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T41	1		T49	2		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1161	1			T15	8		T17	9		T85	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T48	8		T134	10		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T19	1		T48	8		T50	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T218	7		T197	14		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1291	1			T13	2		T17	10		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T26	2		T143	1		T186	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T16	2		T50	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	5		T18	5		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T136	11		T235	1		T184	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T19	1		T230	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T43	5		T266	1		T133	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	2		T44	4		T244	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	6		T45	6		T147	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T139	1		T143	1		T132	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T159	4		T27	3		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T19	1		T158	1		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T146	7		T25	2		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	2		T49	3		T50	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T9	1		T15	9		T134	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T41	2		T135	1		T92	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T234	12		T281	13		T282	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14558	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T48	5		T134	15		T137	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T48	9		T50	11		T229	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T197	13		T232	2		T165	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1403	1			T20	11		T130	42		T261	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T186	11		T218	10		T164	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	13		T231	12		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T18	9		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T136	10		T235	18		T184	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T158	14		T149	13		T176	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	1		T133	17		T172	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T44	1		T243	8		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	1		T144	5		T164	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T132	15		T238	13		T190	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T233	15		T239	13		T271	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T158	12		T148	1		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T132	9		T231	12		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T50	11		T135	15		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T134	10		T136	7		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T135	8		T284	9		T288	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T234	12		T263	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T289	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T279	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T280	14		T222	4		T193	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T138	1		T152	13		T285	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	8		T134	10		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T19	1		T48	8		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T159	15		T150	13		T218	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T16	2		T50	23		T229	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T159	5		T218	1		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T147	12		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T18	5		T26	2		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T136	11		T266	1		T184	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	5		T138	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T43	5		T235	1		T185	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	1		T230	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	6		T45	6		T162	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	2		T44	4		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T147	3		T144	1		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T139	1		T143	1		T148	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	1		T146	7		T132	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T24	2		T19	1		T41	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1524	1			T13	2		T15	9		T17	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T222	11		T193	16		T286	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T138	9		T152	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T48	5		T134	15		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T48	9		T135	3		T144	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T159	14		T197	2		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T50	24		T229	12		T137	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T218	10		T164	5		T255	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T259	15		T183	10		T260	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	9		T186	11		T233	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	10		T184	13		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	2		T138	14		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	1		T235	18		T185	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T158	14		T243	8		T274	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	1		T267	8		T236	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T44	1		T132	15		T238	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T144	5		T164	6		T233	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T148	1		T149	8		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T132	9		T231	12		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T50	11		T135	23		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1444	1			T20	11		T130	42		T261	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11