Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20125

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3825

1

T40

2

T24

2

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17570

1

T3

19

T4

20

T5

8

auto[1]

6380

1

T5

7

T9

1

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	257	1			T5	7		T19	1		T25	2
values[0]	1	1			T290	1		-	-		-	-
values[1]	778	1			T24	2		T50	20		T134	25
values[2]	714	1			T18	14		T137	17		T147	3
values[3]	685	1			T48	13		T49	3		T146	7
values[4]	3179	1			T13	2		T15	9		T17	10
values[5]	478	1			T40	2		T135	4		T158	13
values[6]	807	1			T16	2		T19	1		T50	18
values[7]	841	1			T48	17		T229	27		T136	40
values[8]	841	1			T6	1		T230	1		T135	9
values[9]	815	1			T9	1		T14	6		T50	27
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	653	1			T24	2		T50	20		T45	7
values[1]	789	1			T18	14		T48	13		T135	16
values[2]	797	1			T49	3		T146	7		T136	12
values[3]	3032	1			T13	2		T15	9		T17	10
values[4]	591	1			T40	2		T50	18		T183	11
values[5]	818	1			T16	2		T19	1		T229	27
values[6]	887	1			T48	17		T136	21		T138	15
values[7]	635	1			T6	1		T14	6		T50	27
values[8]	864	1			T5	7		T9	1		T19	1
values[9]	127	1			T280	14		T291	1		T292	24
minimum	14757	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T147	1		T46	1		T232	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T24	2		T50	12		T45	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	10		T48	6		T144	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T135	16		T137	17		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T146	1		T266	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T49	1		T136	8		T259	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T13	2		T15	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T19	1		T41	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T50	12		T151	1		T271	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	2		T183	11		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	2		T19	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T229	13		T136	9		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T136	11		T164	14		T152	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T48	10		T138	15		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T14	1		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T230	1		T135	9		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	5		T9	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T19	1		T25	2		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T280	1		T293	2		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T291	1		T292	14		T191	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14498	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T134	16		T188	1		T294	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T147	2		T292	14		T87	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T50	8		T45	1		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T18	4		T48	7		T173	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	13		T239	16		T236	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	6		T162	4		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T49	2		T136	4		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T15	8		T17	9		T85	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	1		T185	7		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	6		T151	11		T271	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T184	2		T159	3		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T162	2		T184	5		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T229	14		T136	10		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T136	10		T164	6		T152	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	7		T159	14		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	5		T50	13		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T237	1		T239	12		T295	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	2		T131	16		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	1		T147	10		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T280	13		T293	1		T279	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T292	10		T191	14		T296	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T134	9		T294	14		T297	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T5	5		T152	13		T298	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T19	1		T25	2		T148	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	1		T232	10		T173	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T24	2		T50	12		T134	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	10		T147	1		T144	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T137	17		T139	1		T235	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	6		T146	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	1		T135	16		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T13	2		T15	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T19	1		T41	1		T136	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T135	4		T158	13		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	2		T183	11		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T16	2		T19	1		T50	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T244	1		T299	1		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T136	11		T162	1		T184	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T48	10		T229	13		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T147	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T230	1		T135	9		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T14	1		T50	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T44	4		T147	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T5	2		T152	12		T280	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T148	8		T249	10		T191	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T173	14		T236	11		T292	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T50	8		T134	9		T45	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	4		T147	2		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T27	1		T236	21		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	7		T146	6		T162	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	2		T145	13		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T15	8		T17	9		T85	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	1		T136	4		T185	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T151	11		T301	15		T252	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T184	2		T159	3		T150	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T50	6		T271	11		T254	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T244	2		T231	19		T172	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	10		T162	2		T184	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	7		T229	14		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T218	6		T152	6		T246	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T237	1		T239	12		T238	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	5		T50	13		T131	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T44	1		T147	10		T132	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T147	3		T46	1		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	2		T50	9		T45	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T18	5		T48	8		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T135	1		T137	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T146	7		T266	1		T162	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	3		T136	5		T259	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T13	2		T15	9		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	1		T41	2		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	7		T151	12		T271	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T40	2		T183	1		T184	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T16	2		T19	1		T162	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T229	15		T136	11		T244	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T136	11		T164	8		T152	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	8		T138	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	1		T14	6		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T230	1		T135	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	5		T9	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	1		T25	2		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T280	14		T293	2		T279	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T291	1		T292	11		T191	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14600	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T134	10		T188	1		T294	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T232	9		T292	2		T87	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	11		T45	1		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	9		T48	5		T144	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T135	15		T137	16		T235	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T133	17		T186	11		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T136	7		T259	15		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T20	11		T43	1		T130	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T185	12		T243	8		T274	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T50	11		T271	9		T302	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T183	10		T242	10		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T184	13		T267	8		T197	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T229	12		T136	8		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T136	10		T164	12		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T48	9		T138	14		T159	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T50	13		T233	15		T190	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	8		T137	14		T149	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	2		T131	8		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	1		T132	15		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T293	1		T303	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T292	13		T191	12		T193	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T236	17		T284	4		T263	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T134	15		T294	14		T297	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T5	5		T152	13		T298	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T19	1		T25	2		T148	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	1		T232	1		T173	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T24	2		T50	9		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	5		T147	3		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T137	1		T139	1		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	8		T146	7		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	3		T135	1		T145	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T13	2		T15	9		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T19	1		T41	2		T136	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T135	1		T158	1		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	2		T183	1		T184	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	2		T19	1		T50	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T244	3		T299	1		T231	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T136	11		T162	3		T184	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T48	8		T229	15		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	1		T147	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T230	1		T135	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	1		T14	6		T50	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T44	4		T147	11		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T5	2		T152	12		T293	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T148	10		T191	12		T304	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T232	9		T236	17		T292	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T50	11		T134	15		T45	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T18	9		T144	16		T133	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T137	16		T235	18		T158	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	5		T234	12		T152	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T135	15		T132	9		T239	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T20	11		T43	1		T130	42
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T136	7		T259	15		T185	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T135	3		T158	12		T302	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T183	10		T242	10		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	11		T267	8		T271	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T231	12		T172	21		T305	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	10		T184	13		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	9		T229	12		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T233	15		T152	9		T190	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T135	8		T137	14		T149	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	13		T131	8		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	1		T132	15		T164	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11