Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20495

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3455

1

T5

7

T40

2

T15

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17622

1

T3

19

T4

20

T5

15

auto[1]

6328

1

T6

1

T9

1

T40

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T147	11		T241	11		T306	5
values[0]	37	1			T245	10		T307	8		T263	10
values[1]	617	1			T41	2		T146	7		T138	10
values[2]	600	1			T5	7		T6	1		T9	1
values[3]	563	1			T50	47		T134	25		T266	1
values[4]	739	1			T14	6		T15	9		T136	19
values[5]	3221	1			T13	2		T17	10		T18	14
values[6]	783	1			T16	2		T19	1		T48	17
values[7]	584	1			T137	17		T183	11		T185	20
values[8]	695	1			T40	2		T19	1		T25	2
values[9]	1530	1			T24	2		T49	3		T229	27
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	811	1			T5	7		T41	2		T146	7
values[1]	584	1			T6	1		T9	1		T48	13
values[2]	594	1			T15	9		T50	27		T161	2
values[3]	3078	1			T13	2		T14	6		T17	10
values[4]	825	1			T18	14		T19	1		T137	15
values[5]	720	1			T16	2		T19	1		T48	17
values[6]	620	1			T136	12		T137	17		T45	7
values[7]	770	1			T40	2		T19	1		T49	3
values[8]	1072	1			T24	2		T229	27		T135	9
values[9]	302	1			T139	2		T235	19		T300	1
minimum	14574	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T146	1		T159	15		T242	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	5		T41	1		T131	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T9	1		T48	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T266	1		T143	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T50	14		T151	1		T308	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T15	1		T161	1		T231	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1728	1			T13	2		T14	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T186	12		T242	8		T152	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T18	10		T19	1		T137	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T147	1		T26	2		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	2		T19	1		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T48	10		T43	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T137	17		T45	6		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T136	8		T183	11		T185	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T230	1		T143	1		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T40	2		T19	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T24	2		T229	13		T44	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T135	9		T147	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T235	19		T197	12		T246	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T139	2		T300	1		T234	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14469	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T138	10		T309	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T146	6		T159	14		T242	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	2		T41	1		T131	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	7		T50	8		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T162	4		T132	11		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	13		T151	11		T310	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T15	8		T161	1		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T14	5		T17	9		T85	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T186	14		T242	7		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	4		T162	15		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	2		T132	9		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T50	6		T164	11		T173	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T48	7		T43	1		T271	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T45	1		T184	5		T172	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T136	4		T185	7		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T243	9		T150	12		T161	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T49	2		T134	10		T162	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T229	14		T44	1		T184	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T147	10		T244	2		T159	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T197	12		T246	2		T311	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T234	11		T253	14		T239	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T147	1		T241	6		T306	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T307	4		T263	10		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	1		T159	15		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	1		T138	10		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T9	1		T48	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	5		T131	9		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T50	26		T134	16		T190	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T266	1		T298	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	1		T136	9		T144	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	1		T186	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T13	2		T17	1		T18	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T147	1		T46	1		T231	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T16	2		T19	1		T50	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T48	10		T43	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T137	17		T149	16		T172	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T183	11		T185	13		T267	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T230	1		T45	6		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T40	2		T19	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T24	2		T229	13		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	470	1			T49	1		T135	9		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T147	10		T241	5		T306	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T307	4		T312	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T245	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T146	6		T159	14		T239	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T41	1		T145	13		T295	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	7		T136	10		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	2		T131	16		T162	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T50	21		T134	9		T175	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T313	13		T314	13		T315	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	5		T136	10		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	8		T186	14		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T17	9		T18	4		T85	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	2		T231	19		T164	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T50	6		T184	5		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	7		T43	1		T132	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T172	17		T173	4		T252	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T185	7		T252	15		T316	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T45	1		T243	9		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	10		T136	4		T162	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T229	14		T44	1		T184	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T49	2		T244	2		T159	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T146	7		T159	15		T242	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	5		T41	2		T131	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T9	1		T48	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T266	1		T143	1		T162	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T50	14		T151	12		T308	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T15	9		T161	2		T231	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T13	2		T14	6		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T186	15		T242	8		T152	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T18	5		T19	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T147	3		T26	2		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	2		T19	1		T50	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	8		T43	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T137	1		T45	6		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T136	5		T183	1		T185	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T230	1		T143	1		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	2		T19	1		T49	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T24	2		T229	15		T44	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T135	1		T147	11		T244	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T235	1		T197	13		T246	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T139	2		T300	1		T234	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14555	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T138	1		T309	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T159	14		T242	10		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	2		T131	8		T233	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	5		T50	11		T135	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T132	9		T149	8		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	13		T308	4		T310	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T231	12		T278	5		T317	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T20	11		T130	42		T261	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T186	11		T242	7		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	9		T137	14		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T132	15		T231	12		T164	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	11		T135	3		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T48	9		T43	1		T267	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T137	16		T45	1		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	7		T183	10		T185	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T243	8		T149	13		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T134	10		T158	14		T133	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T229	12		T44	1		T152	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T135	8		T161	14		T260	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T235	18		T197	11		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T234	12		T239	13		T275	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T303	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T138	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T147	11		T241	6		T306	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T307	5		T263	1		T312	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T245	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	7		T159	15		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T41	2		T138	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T9	1		T48	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	5		T131	17		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T50	23		T134	10		T190	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T266	1		T298	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	6		T136	11		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	9		T186	15		T161	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T13	2		T17	10		T18	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T147	3		T46	1		T231	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	2		T19	1		T50	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	8		T43	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T137	1		T149	1		T172	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T183	1		T185	8		T267	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T230	1		T45	6		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	2		T19	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T24	2		T229	15		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T49	3		T135	1		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T241	5		T306	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T307	3		T263	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T159	14		T239	10		T287	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T138	9		T233	15		T318	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	5		T135	15		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	2		T131	8		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	24		T134	15		T190	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T278	5		T315	7		T263	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T136	8		T144	21		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T186	11		T231	12		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T18	9		T20	11		T130	42
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T231	12		T164	5		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	11		T135	3		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	9		T43	1		T132	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	16		T149	15		T172	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T183	10		T185	12		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T45	1		T243	8		T149	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T134	10		T136	7		T133	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T229	12		T44	1		T235	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T135	8		T158	14		T234	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11