Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19916

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

4034

1

T5

7

T40

2

T14

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17818

1

T3

19

T4

20

T5

8

auto[1]

6132

1

T5

7

T40

2

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	292	1			T138	15		T132	21		T159	5
values[0]	3	1			T252	3		-	-		-	-
values[1]	843	1			T41	2		T43	6		T136	12
values[2]	591	1			T48	13		T137	32		T300	1
values[3]	782	1			T9	1		T15	9		T25	2
values[4]	744	1			T40	2		T49	3		T136	19
values[5]	923	1			T6	1		T18	14		T229	27
values[6]	575	1			T50	18		T134	25		T135	4
values[7]	477	1			T16	2		T19	1		T146	7
values[8]	786	1			T5	7		T24	2		T14	6
values[9]	3380	1			T13	2		T17	10		T19	2
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T41	2		T43	6		T136	12
values[1]	703	1			T48	13		T25	2		T143	1
values[2]	657	1			T9	1		T15	9		T136	19
values[3]	867	1			T40	2		T49	3		T135	9
values[4]	838	1			T6	1		T18	14		T229	27
values[5]	584	1			T50	18		T134	25		T135	4
values[6]	2871	1			T13	2		T16	2		T17	10
values[7]	776	1			T5	7		T24	2		T14	6
values[8]	896	1			T19	2		T48	17		T50	47
values[9]	268	1			T134	21		T162	5		T237	5
minimum	14715	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	1		T43	5		T136	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T137	32		T132	16		T183	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T48	6		T143	1		T259	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	2		T162	1		T231	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	1		T136	9		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	1		T147	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T135	9		T158	13		T131	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T40	2		T49	1		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	1		T18	10		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T229	13		T188	1		T234	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	12		T134	16		T135	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	4		T136	11		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T13	2		T16	2		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	1		T144	17		T186	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T24	2		T230	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T5	5		T14	1		T135	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T19	2		T48	10		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	14		T45	6		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T162	1		T267	9		T236	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T134	11		T237	4		T239	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14501	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T249	1		T319	1		T252	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	1		T43	1		T136	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T132	9		T172	17		T238	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	7		T148	8		T253	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T162	15		T231	19		T239	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	10		T164	4		T197	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	8		T147	10		T162	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	16		T151	11		T173	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	2		T175	4		T295	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T18	4		T184	2		T165	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T229	14		T234	11		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T50	6		T134	9		T133	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T44	1		T136	10		T147	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T17	9		T85	7		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T186	14		T27	1		T320	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T148	5		T159	3		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T5	2		T14	5		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	7		T50	8		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T50	13		T45	1		T152	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T162	4		T236	11		T247	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T134	10		T237	1		T239	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T249	10		T252	2		T321	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T138	15		T132	10		T159	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T237	4		T245	1		T194	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T41	1		T43	5		T136	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T132	16		T183	11		T172	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	6		T300	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T137	32		T162	1		T231	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T148	11		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	1		T25	2		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	9		T158	13		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	2		T49	1		T206	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	1		T18	10		T135	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T229	13		T234	13		T149	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T50	12		T134	16		T135	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	4		T188	1		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T16	2		T146	1		T149	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	1		T136	11		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T24	2		T230	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T5	5		T14	1		T135	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1754	1			T13	2		T17	1		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T50	14		T134	11		T45	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T132	11		T159	4		T161	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T237	1		T245	8		T194	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T252	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T41	1		T43	1		T136	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T132	9		T172	17		T238	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	7		T271	10		T322	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T162	15		T231	19		T239	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T148	8		T253	14		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	8		T147	10		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T136	10		T151	11		T239	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	2		T254	6		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T18	4		T131	16		T184	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T229	14		T234	11		T245	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T50	6		T134	9		T133	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T44	1		T243	9		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T146	6		T271	11		T175	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T136	10		T147	2		T186	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T159	3		T258	14		T173	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T5	2		T14	5		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T17	9		T85	7		T48	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T50	13		T134	10		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	2		T43	5		T136	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T137	2		T132	10		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T48	8		T143	1		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T25	2		T162	16		T231	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	1		T136	11		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	9		T147	11		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T135	1		T158	1		T131	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	2		T49	3		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	1		T18	5		T184	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T229	15		T188	1		T234	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	7		T134	10		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T44	4		T136	11		T147	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T13	2		T16	2		T17	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	1		T144	1		T186	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T24	2		T230	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T5	5		T14	6		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T19	2		T48	8		T50	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T50	14		T45	6		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T162	5		T267	1		T236	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T134	11		T237	4		T239	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14568	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T249	11		T319	1		T252	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T43	1		T136	7		T242	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T137	30		T132	15		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	5		T259	15		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T231	12		T232	9		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T136	8		T164	5		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T184	13		T185	12		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T135	8		T158	12		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T175	6		T241	14		T106	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T18	9		T233	15		T165	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T229	12		T234	12		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	11		T134	15		T135	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T44	1		T136	10		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T20	11		T130	42		T261	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T144	16		T186	11		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T148	1		T164	6		T262	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	2		T135	15		T235	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T48	9		T50	11		T138	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	13		T45	1		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T267	8		T236	17		T247	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T134	10		T237	1		T239	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T144	5		T164	7		T95	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T321	17		T195	12		T323	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T138	1		T132	12		T159	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T237	4		T245	9		T194	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T252	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T41	2		T43	5		T136	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T132	10		T183	1		T172	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	8		T300	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T137	2		T162	16		T231	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	1		T148	9		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	9		T25	2		T147	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T136	11		T158	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	2		T49	3		T206	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T18	5		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T229	15		T234	12		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	7		T134	10		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T44	4		T188	1		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	2		T146	7		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T19	1		T136	11		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T24	2		T230	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T5	5		T14	6		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T13	2		T17	10		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T50	14		T134	11		T45	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T138	14		T132	9		T267	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T237	1		T194	9		T263	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	1		T136	7		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T132	15		T183	10		T172	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	5		T259	15		T218	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T137	30		T231	12		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	10		T164	5		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T184	13		T185	12		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T136	8		T158	12		T233	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T175	6		T106	6		T195	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T18	9		T135	8		T131	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T229	12		T234	12		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T50	11		T134	15		T135	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T44	1		T243	8		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T149	8		T197	2		T232	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	10		T186	11		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T246	7		T89	14		T324	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	2		T135	15		T144	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T20	11		T48	9		T50	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T50	13		T134	10		T45	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11