Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20491

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3459

1

T5

7

T40

2

T15

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17565

1

T3

19

T4

20

T5

15

auto[1]

6385

1

T6

1

T9

1

T40

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T229	27		T44	5		T147	11
values[0]	9	1			T312	9		-	-		-	-
values[1]	665	1			T41	2		T146	7		T138	10
values[2]	585	1			T5	7		T6	1		T9	1
values[3]	535	1			T50	47		T134	25		T298	1
values[4]	738	1			T14	6		T15	9		T136	19
values[5]	3268	1			T13	2		T17	10		T18	14
values[6]	784	1			T16	2		T19	1		T48	17
values[7]	559	1			T137	17		T147	1		T183	11
values[8]	702	1			T40	2		T19	1		T25	2
values[9]	1197	1			T24	2		T49	3		T135	9
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T5	7		T41	2		T146	7
values[1]	542	1			T6	1		T9	1		T48	13
values[2]	623	1			T15	9		T50	27		T134	25
values[3]	3065	1			T13	2		T14	6		T17	10
values[4]	883	1			T18	14		T19	1		T147	3
values[5]	660	1			T16	2		T19	1		T48	17
values[6]	669	1			T136	12		T137	17		T147	1
values[7]	754	1			T40	2		T19	1		T49	3
values[8]	1065	1			T24	2		T229	27		T135	9
values[9]	291	1			T139	2		T235	19		T300	1
minimum	14681	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T146	1		T159	15		T242	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	5		T41	1		T131	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T9	1		T48	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T266	1		T143	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T50	14		T134	16		T218	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T15	1		T161	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T13	2		T14	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T186	12		T231	13		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T18	10		T19	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T147	1		T46	1		T132	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	2		T19	1		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	10		T43	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T137	17		T147	1		T243	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	8		T183	11		T185	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T230	1		T45	6		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T40	2		T19	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T24	2		T229	13		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T147	1		T244	1		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T235	19		T197	12		T325	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T139	2		T300	1		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14499	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	10		T281	10		T326	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	6		T159	14		T242	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	2		T41	1		T131	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	7		T50	8		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T162	4		T132	11		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T50	13		T134	9		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T15	8		T161	1		T173	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T14	5		T17	9		T85	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T186	14		T231	12		T258	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	4		T162	15		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T147	2		T132	9		T231	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T50	6		T184	5		T164	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T48	7		T43	1		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T243	9		T172	17		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T136	4		T185	7		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T45	1		T150	12		T161	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	2		T134	10		T162	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T229	14		T44	1		T184	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T147	10		T244	2		T159	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T197	12		T317	16		T327	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T253	14		T301	15		T322	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T281	13		T326	15		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T229	13		T44	4		T299	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T147	1		T139	2		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T146	1		T159	15		T242	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T41	1		T138	10		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T9	1		T48	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	5		T131	9		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T50	26		T134	16		T236	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T298	1		T215	1		T322	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T14	1		T136	9		T144	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	1		T186	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1744	1			T13	2		T17	1		T18	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T147	1		T46	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T16	2		T19	1		T50	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T48	10		T43	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T137	17		T147	1		T149	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T183	11		T185	13		T267	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T230	1		T45	6		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	2		T19	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T24	2		T135	9		T235	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T49	1		T158	15		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T229	14		T44	1		T328	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T147	10		T159	4		T301	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T312	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T146	6		T159	14		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	1		T145	13		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T48	7		T136	10		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	2		T131	16		T162	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T50	21		T134	9		T236	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T322	4		T313	13		T314	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	5		T136	10		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	8		T186	14		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T17	9		T18	4		T85	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T147	2		T218	6		T231	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T50	6		T184	5		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	7		T43	1		T132	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T172	17		T252	2		T329	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T185	7		T252	15		T330	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T45	1		T243	9		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T134	10		T136	4		T162	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T184	2		T152	10		T197	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T49	2		T244	2		T234	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T146	7		T159	15		T242	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	5		T41	2		T131	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	1		T9	1		T48	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T266	1		T143	1		T162	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T50	14		T134	10		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T15	9		T161	2		T173	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T13	2		T14	6		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T186	15		T231	13		T258	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T18	5		T19	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T147	3		T46	1		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	2		T19	1		T50	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	8		T43	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	1		T147	1		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	5		T183	1		T185	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T230	1		T45	6		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	2		T19	1		T49	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T24	2		T229	15		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T147	11		T244	3		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T235	1		T197	13		T325	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T139	2		T300	1		T253	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14585	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T138	1		T281	14		T326	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T159	14		T242	10		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	2		T131	8		T233	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	5		T50	11		T135	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T132	9		T149	8		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	13		T134	15		T218	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T278	5		T317	11		T263	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T20	11		T130	42		T261	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T186	11		T231	12		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T18	9		T144	5		T259	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T132	15		T231	12		T164	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	11		T135	3		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	9		T43	1		T267	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T137	16		T243	8		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T136	7		T183	10		T185	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T45	1		T149	13		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T134	10		T158	14		T133	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T229	12		T135	8		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T234	12		T161	14		T260	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T235	18		T197	11		T331	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T332	12		T333	2		T334	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T199	9		T303	22		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T138	9		T281	9		T326	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T229	15		T44	4		T299	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T147	11		T139	2		T159	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T312	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T146	7		T159	15		T242	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T41	2		T138	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T9	1		T48	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	5		T131	17		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T50	23		T134	10		T236	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T298	1		T215	1		T322	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	6		T136	11		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	9		T186	15		T161	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T13	2		T17	10		T18	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T147	3		T46	1		T218	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	2		T19	1		T50	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	8		T43	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	1		T147	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T183	1		T185	8		T267	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T230	1		T45	6		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	2		T19	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T24	2		T135	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T49	3		T158	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T229	12		T44	1		T331	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T260	12		T335	9		T336	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T159	14		T242	10		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	9		T233	15		T318	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	5		T135	15		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	2		T131	8		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	24		T134	15		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T278	5		T315	7		T317	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T136	8		T144	21		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T186	11		T231	12		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T18	9		T20	11		T130	42
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T231	12		T164	5		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	11		T135	3		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	9		T43	1		T132	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	16		T149	15		T172	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T183	10		T185	12		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T45	1		T243	8		T149	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	10		T136	7		T133	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T135	8		T235	18		T152	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T158	14		T234	12		T161	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11