Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20101

1

T3

19

T4

20

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3849

1

T5

7

T40

2

T24

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17841

1

T3

19

T4

20

T5

15

auto[1]

6109

1

T9

1

T40

2

T13

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T41	2		T337	3		T303	9
values[0]	81	1			T163	1		T165	32		T291	1
values[1]	699	1			T5	7		T14	6		T48	13
values[2]	971	1			T15	9		T18	14		T230	1
values[3]	659	1			T136	12		T137	15		T131	25
values[4]	673	1			T25	2		T135	16		T147	3
values[5]	610	1			T16	2		T146	7		T136	21
values[6]	731	1			T19	1		T48	17		T49	3
values[7]	641	1			T24	2		T19	1		T50	18
values[8]	3192	1			T13	2		T17	10		T20	12
values[9]	1125	1			T6	1		T9	1		T40	2
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1095	1			T5	7		T14	6		T15	9
values[1]	897	1			T230	1		T44	5		T147	11
values[2]	500	1			T136	12		T137	15		T158	15
values[3]	853	1			T16	2		T146	7		T25	2
values[4]	600	1			T134	21		T135	4		T139	1
values[5]	690	1			T24	2		T19	2		T48	17
values[6]	2980	1			T13	2		T17	10		T20	12
values[7]	721	1			T50	20		T135	9		T138	15
values[8]	824	1			T6	1		T9	1		T40	2
values[9]	234	1			T138	10		T143	1		T320	14
minimum	14556	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T14	1		T15	1		T18	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T5	5		T229	13		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T230	1		T44	4		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T147	1		T131	9		T260	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	8		T137	15		T158	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T148	2		T159	1		T218	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T16	2		T146	1		T135	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T25	2		T136	11		T45	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T135	4		T139	1		T186	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	11		T46	1		T159	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	10		T49	1		T162	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	2		T19	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T13	2		T17	1		T20	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T149	16		T151	1		T172	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T135	9		T143	1		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T50	12		T138	15		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	1		T9	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	2		T136	9		T137	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T320	8		T338	1		T339	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T138	10		T143	1		T175	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14461	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T163	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	5		T15	8		T18	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	2		T229	14		T234	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T44	1		T173	4		T271	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T147	10		T131	16		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T136	4		T164	2		T239	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T148	5		T159	4		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	6		T147	2		T133	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T136	10		T45	1		T148	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T186	14		T150	5		T161	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T134	10		T159	14		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T48	7		T49	2		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T184	2		T253	14		T239	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T17	9		T85	7		T50	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T151	11		T172	17		T275	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T258	14		T197	12		T256	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	8		T242	17		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	1		T50	13		T184	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	10		T244	2		T162	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T320	6		T340	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T175	13		T281	13		T329	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T41	1		T303	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T337	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T333	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T163	1		T165	15		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	1		T48	6		T43	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	5		T229	13		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T15	1		T18	10		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T147	1		T260	13		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T136	8		T137	15		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	9		T148	2		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	16		T147	1		T158	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T25	2		T158	13		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	2		T146	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T136	11		T45	6		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T48	10		T49	1		T135	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T19	1		T134	11		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T50	12		T134	16		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	2		T19	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T13	2		T17	1		T20	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T50	12		T144	17		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	1		T9	1		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T40	2		T136	9		T137	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T41	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T165	17		T332	15		T341	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	5		T48	7		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	2		T229	14		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	8		T18	4		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T147	10		T249	10		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	4		T164	2		T239	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	16		T148	5		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T147	2		T133	18		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T159	3		T238	15		T271	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T146	6		T150	5		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	10		T45	1		T184	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	7		T49	2		T145	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T134	10		T253	14		T239	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T50	6		T134	9		T132	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T275	13		T292	14		T91	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T17	9		T85	7		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T50	8		T151	11		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	13		T184	5		T185	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T136	10		T244	2		T162	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T14	6		T15	9		T18	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T5	5		T229	15		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T230	1		T44	4		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T147	11		T131	17		T260	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	5		T137	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T148	6		T159	5		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	2		T146	7		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T25	2		T136	11		T45	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T135	1		T139	1		T186	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	11		T46	1		T159	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T48	8		T49	3		T162	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T24	2		T19	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T13	2		T17	10		T20	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T149	1		T151	12		T172	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	1		T143	1		T258	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	9		T138	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	1		T9	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	2		T136	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T320	7		T338	1		T339	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T138	1		T143	1		T175	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14555	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T163	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T18	9		T48	5		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	2		T229	12		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	1		T235	18		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T131	8		T260	12		T236	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T136	7		T137	14		T158	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T148	1		T218	10		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T135	15		T144	5		T133	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T136	10		T45	1		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T135	3		T186	11		T164	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T134	10		T159	14		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	9		T259	15		T132	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T239	13		T214	8		T294	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T20	11		T50	11		T130	42
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T149	15		T172	21		T233	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	8		T233	9		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T50	11		T138	14		T144	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T50	13		T184	13		T185	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	8		T137	16		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T320	7		T339	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T138	9		T175	10		T281	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T41	2		T303	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T337	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T333	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T163	1		T165	18		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	6		T48	8		T43	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	5		T229	15		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T15	9		T18	5		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T147	11		T260	1		T249	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T136	5		T137	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T131	17		T148	6		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T135	1		T147	3		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	2		T158	1		T159	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	2		T146	7		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T136	11		T45	6		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T48	8		T49	3		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	1		T134	11		T253	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	7		T134	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	2		T19	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T13	2		T17	10		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T50	9		T144	1		T151	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	1		T9	1		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T40	2		T136	11		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T303	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T337	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T333	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T165	14		T332	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	5		T43	1		T235	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	2		T229	12		T234	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T18	9		T44	1		T271	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T260	12		T236	17		T268	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T136	7		T137	14		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T131	8		T148	1		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T135	15		T158	14		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T158	12		T274	14		T238	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T238	4		T241	17		T195	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	10		T45	1		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T48	9		T135	3		T186	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T134	10		T239	13		T214	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	11		T134	15		T259	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T149	15		T161	14		T308	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T20	11		T130	42		T261	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	11		T144	16		T172	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T50	13		T184	13		T185	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T136	8		T137	16		T138	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11