Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23950

1

T3

19

T4

20

T5

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20291

1

T3

19

T4

20

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3659

1

T9

1

T40

2

T14

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17673

1

T3

19

T4

20

T5

15

auto[1]

6277

1

T40

2

T13

2

T24

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T3

19

T4

20

T5

12

auto[1]

3989

1

T5

3

T14

5

T15

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	410	1			T136	21		T231	25		T237	5
values[0]	27	1			T91	10		T92	1		T328	15
values[1]	865	1			T230	1		T138	15		T139	1
values[2]	665	1			T16	2		T18	14		T48	30
values[3]	741	1			T41	2		T134	25		T229	27
values[4]	697	1			T5	7		T135	9		T44	5
values[5]	3010	1			T13	2		T17	10		T20	12
values[6]	751	1			T19	1		T49	3		T50	27
values[7]	664	1			T9	1		T40	2		T14	6
values[8]	720	1			T136	12		T139	1		T266	1
values[9]	846	1			T6	1		T24	2		T15	9
minimum	14554	1			T3	19		T4	20		T5	8

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	812	1			T18	14		T230	1		T138	15
values[1]	663	1			T16	2		T48	30		T144	6
values[2]	823	1			T5	7		T41	2		T134	25
values[3]	3044	1			T13	2		T17	10		T20	12
values[4]	613	1			T19	1		T50	27		T137	17
values[5]	687	1			T40	2		T49	3		T43	6
values[6]	759	1			T9	1		T14	6		T19	1
values[7]	707	1			T6	1		T136	12		T137	15
values[8]	931	1			T24	2		T15	9		T19	1
values[9]	142	1			T231	25		T319	1		T342	37
minimum	14769	1			T3	19		T4	20		T5	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

4512

1

T5

2

T18

9

T20

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T18	10		T230	1		T138	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T158	13		T300	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	2		T144	6		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	16		T186	12		T161	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	5		T41	1		T229	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T134	16		T136	9		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1732	1			T13	2		T17	1		T20	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T135	16		T44	4		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T19	1		T50	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	17		T26	2		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	1		T43	5		T135	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	2		T25	2		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T139	2		T159	1		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T14	1		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T136	8		T137	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T145	1		T259	16		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	2		T132	16		T149	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T15	1		T19	1		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T231	13		T241	6		T321	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T319	1		T342	27		T343	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14498	1			T3	19		T4	20		T5	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T149	9		T218	1		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	4		T159	3		T150	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T162	15		T234	11		T271	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T132	11		T27	1		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	14		T186	14		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	2		T41	1		T229	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	9		T136	10		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T17	9		T85	7		T50	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	1		T184	5		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T50	13		T147	2		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T162	2		T95	14		T329	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	2		T43	1		T249	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T231	19		T172	17		T280	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T159	4		T197	12		T236	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	5		T146	6		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	4		T161	1		T258	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	13		T148	5		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T132	9		T150	5		T173	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T15	8		T50	8		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T231	12		T241	5		T321	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T342	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	1		T43	2		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T218	6		T152	12		T257	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T231	13		T238	14		T325	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	11		T237	4		T232	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T91	1		T92	1		T328	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T230	1		T138	15		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T300	1		T143	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	2		T18	10		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T48	16		T158	13		T234	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T41	1		T229	13		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	16		T45	6		T131	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	5		T135	9		T235	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	4		T136	9		T158	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1719	1			T13	2		T17	1		T20	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T135	16		T137	17		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T19	1		T49	1		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T25	2		T138	10		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T43	5		T139	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	1		T40	2		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T136	8		T139	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T266	1		T163	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	1		T24	2		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T15	1		T19	1		T50	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14460	1			T3	19		T4	20		T5	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T231	12		T238	15		T321	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T136	10		T237	1		T344	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T91	9		T328	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T159	3		T150	12		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T162	15		T218	6		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T18	4		T151	11		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	14		T234	11		T238	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T41	1		T229	14		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T134	9		T45	1		T131	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	2		T244	2		T161	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T44	1		T136	10		T184	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T17	9		T85	7		T50	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T162	2		T243	9		T164	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	2		T50	13		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T231	19		T172	17		T280	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	1		T305	13		T256	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	5		T146	6		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T136	4		T159	4		T258	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T301	15		T246	9		T313	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T132	9		T150	5		T161	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	8		T50	8		T145	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T43	2		T44	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T18	5		T230	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T158	1		T300	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	2		T144	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T48	16		T186	15		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	5		T41	2		T229	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T134	10		T136	11		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T13	2		T17	10		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T135	1		T44	4		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T19	1		T50	14		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T137	1		T26	2		T162	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	3		T43	5		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T40	2		T25	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T139	2		T159	5		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T14	6		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T136	5		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T145	14		T259	1		T148	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	2		T132	10		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T15	9		T19	1		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T231	13		T241	6		T321	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T319	1		T342	11		T343	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14579	1			T3	19		T4	20		T5	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T149	1		T218	7		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T18	9		T138	14		T149	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T158	12		T234	12		T271	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	5		T132	9		T164	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	14		T186	11		T161	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	2		T229	12		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T134	15		T136	8		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T20	11		T50	11		T130	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	15		T44	1		T184	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	13		T144	16		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	16		T95	16		T284	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	1		T135	3		T305	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T138	9		T231	12		T172	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T197	11		T236	7		T302	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T134	10		T185	12		T294	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T136	7		T137	14		T260	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T259	15		T148	1		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T132	15		T149	15		T233	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T50	11		T136	10		T159	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T231	12		T241	5		T321	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T342	26		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T176	9		T283	9		T331	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T149	8		T152	12		T257	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T231	13		T238	16		T325	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T136	11		T237	4		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T91	10		T92	1		T328	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T230	1		T138	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T300	1		T143	1		T162	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	2		T18	5		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	16		T158	1		T234	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T41	2		T229	15		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T134	10		T45	6		T131	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	5		T135	1		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T44	4		T136	11		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T13	2		T17	10		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	1		T137	1		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T19	1		T49	3		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T25	2		T138	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T43	5		T139	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T40	2		T14	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T136	5		T139	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T266	1		T163	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T24	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	9		T19	1		T50	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T3	19		T4	20		T5	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T231	12		T238	13		T321	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T136	10		T237	1		T232	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T328	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T138	14		T149	13		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T149	8		T152	12		T257	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T18	9		T144	5		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	14		T158	12		T234	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T229	12		T132	9		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T134	15		T45	1		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	2		T135	8		T235	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	1		T136	8		T158	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T20	11		T50	11		T130	42
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T135	15		T137	16		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T50	13		T135	3		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T138	9		T231	12		T172	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T43	1		T305	13		T302	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T134	10		T185	12		T294	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T136	7		T260	12		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T246	13		T278	10		T281	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T137	14		T132	15		T149	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T50	11		T259	15		T148	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19438

1

T3

19

T4

20

T5

13

auto[1]

auto[0]

4512

1

T5

2

T18

9

T20

11