Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6094	1			T1	20		T4	7		T5	20
testmodes[AdcCtrlTestmodeNormal]	5393	1			T4	3		T7	3		T8	9
testmodes[AdcCtrlTestmodeLowpower]	5640	1			T6	17		T7	1		T9	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2846	1			T1	19		T4	4		T5	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1697	1			T4	3		T7	1		T8	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1433	1			T9	1		T12	1		T13	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1688	1			T4	2		T8	4		T9	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1920	1			T7	2		T8	4		T9	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1442	1			T7	1		T12	1		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1440	1			T14	1		T68	10		T63	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1443	1			T9	1		T12	2		T13	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2519	1			T6	16		T11	9		T12	1