Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.07	96.67	100.00	100.00	98.83	98.33	91.49

Total tests in report: 919

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
71.95	71.95	97.22	97.22	81.10	81.10	88.39	88.39	43.24	43.24	95.43	95.43	85.14	85.14	13.10	13.10	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3846099940
78.01	6.06	98.24	1.02	85.30	4.20	89.81	1.42	70.27	27.03	97.22	1.79	87.98	2.84	17.22	4.12	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2724059626
81.72	3.71	98.27	0.03	85.67	0.37	92.65	2.84	91.89	21.62	97.34	0.12	87.98	0.00	18.22	1.00	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.1819166794
84.84	3.12	98.77	0.49	92.51	6.83	97.63	4.98	91.89	0.00	98.15	0.80	90.65	2.67	24.26	6.04	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1885295654
86.54	1.71	98.77	0.00	92.51	0.00	97.63	0.00	100.00	8.11	98.15	0.00	90.82	0.17	27.93	3.67	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.4190378083
88.02	1.48	98.89	0.12	92.71	0.21	97.63	0.00	100.00	0.00	98.33	0.19	91.65	0.83	36.91	8.98	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3820358033
89.35	1.33	98.89	0.00	94.24	1.52	97.63	0.00	100.00	0.00	98.58	0.25	91.65	0.00	44.45	7.54	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3909640159
90.39	1.04	98.89	0.00	94.24	0.00	97.63	0.00	100.00	0.00	98.58	0.00	91.99	0.33	51.39	6.94	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.442064364
91.24	0.85	98.89	0.00	94.24	0.00	97.63	0.00	100.00	0.00	98.58	0.00	95.99	4.01	53.36	1.97	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1979627327
91.97	0.73	98.89	0.00	94.28	0.04	97.63	0.00	100.00	0.00	98.58	0.00	95.99	0.00	58.45	5.09	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.3297648565
92.51	0.53	98.89	0.00	94.28	0.00	97.63	0.00	100.00	0.00	98.58	0.00	95.99	0.00	62.19	3.74	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2603395011
92.99	0.48	98.89	0.00	94.28	0.00	97.63	0.00	100.00	0.00	98.58	0.00	95.99	0.00	65.54	3.34	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1366238800
93.44	0.45	98.92	0.03	94.40	0.12	99.76	2.13	100.00	0.00	98.64	0.06	96.66	0.67	65.66	0.12	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.60898354
93.85	0.41	98.92	0.00	94.40	0.00	99.76	0.00	100.00	0.00	98.64	0.00	96.66	0.00	68.53	2.87	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2472457868
94.17	0.33	98.92	0.00	94.48	0.08	99.76	0.00	100.00	0.00	98.64	0.00	96.66	0.00	70.73	2.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3514793407
94.48	0.31	98.92	0.00	94.48	0.00	99.76	0.00	100.00	0.00	98.64	0.00	96.66	0.00	72.92	2.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.646558051
94.76	0.28	98.92	0.00	95.72	1.24	99.76	0.00	100.00	0.00	98.70	0.06	96.99	0.33	73.25	0.32	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.188475223
95.03	0.26	98.92	0.00	95.72	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.99	0.00	75.09	1.85	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.1687942227
95.28	0.25	98.92	0.00	95.72	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.99	0.00	76.84	1.75	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1604814388
95.52	0.24	98.92	0.00	95.72	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.99	0.00	78.51	1.67	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1758092651
95.70	0.18	98.98	0.06	95.97	0.25	99.76	0.00	100.00	0.00	98.83	0.12	97.83	0.83	78.51	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4190924339
95.88	0.18	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	79.76	1.25	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.1767135854
96.04	0.16	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	80.91	1.15	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3619411215
96.19	0.15	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	81.96	1.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.210900697
96.32	0.13	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	82.86	0.90	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.1275243305
96.43	0.11	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	83.65	0.80	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.830642141
96.52	0.09	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	84.30	0.65	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.2970167020
96.61	0.08	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	84.88	0.57	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3420796124
96.68	0.08	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.83	0.00	85.43	0.55	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.2064836197
96.76	0.07	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.50	85.43	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3882391020
96.83	0.07	98.98	0.00	95.97	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.92	0.50	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.3910766832
96.89	0.06	99.07	0.09	96.09	0.12	100.00	0.24	100.00	0.00	98.83	0.00	98.33	0.00	85.92	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3799979149
96.96	0.06	99.07	0.00	96.34	0.25	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.12	0.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3479096591
97.01	0.06	99.07	0.00	96.54	0.21	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.32	0.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3622653952
97.07	0.05	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.70	0.37	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2573727223
97.11	0.05	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.02	0.32	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.4079331647
97.16	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.32	0.30	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3549391986
97.20	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.62	0.30	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1564603747
97.24	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.90	0.27	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.2141822816
97.27	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.15	0.25	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.2445214148
97.31	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.40	0.25	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1464428842
97.34	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.59	0.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3280417132
97.37	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.79	0.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.3794363562
97.40	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.99	0.20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.2783469732
97.42	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.14	0.15	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1016174558
97.44	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.29	0.15	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.1093265196
97.46	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.44	0.15	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2484986234
97.48	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.59	0.15	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.508236279
97.50	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.72	0.12	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.1079350590
97.52	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.84	0.12	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.4018835681
97.53	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.94	0.10	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2179037475
97.54	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.04	0.10	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3553249188
97.56	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.14	0.10	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.2808032175
97.57	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.24	0.10	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3876509590
97.59	0.01	99.07	0.00	96.62	0.08	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.24	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.279935181
97.60	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.32	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3949155783
97.61	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.39	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.4085668672
97.62	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.47	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1095312322
97.63	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.54	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.2577445931
97.64	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.62	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1611184318
97.65	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.69	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.1390474391
97.66	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.77	0.07	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1895844381
97.67	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.82	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2994304074
97.67	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.87	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2222742035
97.68	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.92	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3626336403
97.69	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.97	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.1067889069
97.70	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.02	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.856105770
97.70	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.07	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.2568528234
97.71	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.12	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1038161421
97.72	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.17	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2328831232
97.72	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.22	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.3833327738
97.73	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.27	0.05	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.576372615
97.74	0.01	99.07	0.00	96.67	0.04	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.27	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.675696808
97.74	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.29	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1959530493
97.74	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.32	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1556981989
97.75	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.34	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1238598537
97.75	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.37	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.1381107101
97.76	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.39	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.1354711367
97.76	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.42	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.713017339
97.76	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.44	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.2278572710
97.77	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.46	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.1026079437
97.77	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.49	0.02	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3547330676

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2468654552
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1713771863
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.609929694
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.979733216
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2050861907
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2251860465
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2989718772
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.863296866
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2220585975
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3853313830
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1544447256
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4198058733
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3389067859
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1006269331
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.539720443
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1567277630
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2728217873
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1677352864
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2461077698
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2820359714
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2297667012
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2847203594
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.1808691757
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2073139535
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1302950289
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1003577152
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3244609875
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2708291795
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3573497707
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1561427176
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.415002484
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1614744493
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2303005116
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.217782496
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.543822904
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2607057062
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3326163511
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.124329761
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2608216772
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2931900826
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3640683178
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1746399053
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2425711262
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3805013757
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2908600829
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.1119371250
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1824727420
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1168424448
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4152702762
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.643458634
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3639775963
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.3560471806
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2391540282
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2834203749
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1721288917
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3782112876
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.165212265
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.745443205
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3878875011
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.577953154
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.152472755
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4240191881
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2505440672
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.2239989097
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4272227406
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2979350486
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2536879907
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2214451088
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.304863325
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.782476717
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1068872965
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2279177335
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2532827570
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2766198114
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2765447505
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1213107786
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1801244991
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3214343050
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3950978635
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1847147546
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3346656093
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2810434691
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.539061734
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4069385225
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3280640880
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3125788056
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3722084154
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1424333902
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.1902868520
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.626095445
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.797807957
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.71478626
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3274834857
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3028193302
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1715223003
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4082329671
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3007112824
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.139634979
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3527262692
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3451567255
/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.1794161729
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Total test records in report: 919

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.4166630433			Sep 11 03:37:25 AM UTC 24	Sep 11 03:37:34 AM UTC 24	5918871113 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3799979149			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:39 AM UTC 24	418281438 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.341642029			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:40 AM UTC 24	530278199 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.600156576			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:41 AM UTC 24	3108035596 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1341658531			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:42 AM UTC 24	5735276479 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.60898354			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:44 AM UTC 24	8162014058 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.662854226			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:47 AM UTC 24	40554132056 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3846099940			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:47 AM UTC 24	19876640330 ps
T21	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.981399029			Sep 11 03:37:45 AM UTC 24	Sep 11 03:37:47 AM UTC 24	334087261 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.2955634140			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:48 AM UTC 24	3719548319 ps
T22	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.3046385694			Sep 11 03:37:43 AM UTC 24	Sep 11 03:37:49 AM UTC 24	4464550955 ps
T23	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.1766035885			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:49 AM UTC 24	8006500670 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2724059626			Sep 11 03:37:41 AM UTC 24	Sep 11 03:37:50 AM UTC 24	18109567409 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3845331962			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:52 AM UTC 24	5831614464 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2405323599			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:53 AM UTC 24	23276876538 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1616672741			Sep 11 03:37:37 AM UTC 24	Sep 11 03:37:53 AM UTC 24	32151177222 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.4061894664			Sep 11 03:37:39 AM UTC 24	Sep 11 03:37:54 AM UTC 24	4765049570 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3266152227			Sep 11 03:37:47 AM UTC 24	Sep 11 03:37:55 AM UTC 24	5707322247 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.135509121			Sep 11 03:37:57 AM UTC 24	Sep 11 03:37:59 AM UTC 24	584625101 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.3707900479			Sep 11 03:37:52 AM UTC 24	Sep 11 03:38:07 AM UTC 24	2972392712 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1277326222			Sep 11 03:37:52 AM UTC 24	Sep 11 03:38:11 AM UTC 24	32855370946 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.488735982			Sep 11 03:37:55 AM UTC 24	Sep 11 03:38:14 AM UTC 24	3952760665 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3795316666			Sep 11 03:37:55 AM UTC 24	Sep 11 03:38:21 AM UTC 24	30954623803 ps
T88	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.1137439681			Sep 11 03:37:57 AM UTC 24	Sep 11 03:38:21 AM UTC 24	5794447978 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.670458458			Sep 11 03:38:24 AM UTC 24	Sep 11 03:38:27 AM UTC 24	459278084 ps
T96	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.3011251681			Sep 11 03:38:24 AM UTC 24	Sep 11 03:38:29 AM UTC 24	7856397941 ps
T149	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1233586140			Sep 11 03:38:17 AM UTC 24	Sep 11 03:38:30 AM UTC 24	2918373242 ps
T112	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.2038629737			Sep 11 03:38:28 AM UTC 24	Sep 11 03:38:41 AM UTC 24	6030097007 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2980219644			Sep 11 03:38:22 AM UTC 24	Sep 11 03:38:43 AM UTC 24	10602496404 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2282743475			Sep 11 03:38:20 AM UTC 24	Sep 11 03:38:48 AM UTC 24	31504659788 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1885295654			Sep 11 03:37:37 AM UTC 24	Sep 11 03:38:57 AM UTC 24	500826744962 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2753195949			Sep 11 03:38:58 AM UTC 24	Sep 11 03:39:11 AM UTC 24	2889603244 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.3246938252			Sep 11 03:37:39 AM UTC 24	Sep 11 03:39:21 AM UTC 24	40803300478 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3622653952			Sep 11 03:39:12 AM UTC 24	Sep 11 03:39:23 AM UTC 24	6794216811 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.3989208550			Sep 11 03:39:24 AM UTC 24	Sep 11 03:39:26 AM UTC 24	467119478 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.1894253012			Sep 11 03:37:37 AM UTC 24	Sep 11 03:39:32 AM UTC 24	160312577963 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.3329566363			Sep 11 03:39:27 AM UTC 24	Sep 11 03:39:35 AM UTC 24	5774033891 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.869598534			Sep 11 03:38:45 AM UTC 24	Sep 11 03:39:41 AM UTC 24	159042980755 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.4156063707			Sep 11 03:37:37 AM UTC 24	Sep 11 03:40:16 AM UTC 24	166644497266 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3089625363			Sep 11 03:38:10 AM UTC 24	Sep 11 03:40:52 AM UTC 24	335173210680 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2222742035			Sep 11 03:37:36 AM UTC 24	Sep 11 03:41:15 AM UTC 24	206449797171 ps
T102	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1749358637			Sep 11 03:39:00 AM UTC 24	Sep 11 03:41:32 AM UTC 24	37076050033 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.1604306856			Sep 11 03:38:49 AM UTC 24	Sep 11 03:41:35 AM UTC 24	160222504979 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3737901055			Sep 11 03:39:35 AM UTC 24	Sep 11 03:41:38 AM UTC 24	164092788704 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1728514161			Sep 11 03:38:08 AM UTC 24	Sep 11 03:41:42 AM UTC 24	200974848203 ps
T354	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3023020914			Sep 11 03:41:20 AM UTC 24	Sep 11 03:41:43 AM UTC 24	5139019267 ps
T355	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.945167067			Sep 11 03:41:44 AM UTC 24	Sep 11 03:41:46 AM UTC 24	418899948 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.734876115			Sep 11 03:41:39 AM UTC 24	Sep 11 03:41:47 AM UTC 24	20583919460 ps
T97	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.116213551			Sep 11 03:37:35 AM UTC 24	Sep 11 03:41:51 AM UTC 24	165199472197 ps
T137	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3562460081			Sep 11 03:38:04 AM UTC 24	Sep 11 03:42:06 AM UTC 24	406533041816 ps
T356	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.1055260160			Sep 11 03:41:47 AM UTC 24	Sep 11 03:42:08 AM UTC 24	6087910117 ps
T150	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2106512432			Sep 11 03:37:37 AM UTC 24	Sep 11 03:42:09 AM UTC 24	322839505580 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3909640159			Sep 11 03:37:37 AM UTC 24	Sep 11 03:42:21 AM UTC 24	504376869795 ps
T208	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2455242725			Sep 11 03:37:59 AM UTC 24	Sep 11 03:42:29 AM UTC 24	165566202242 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.1819166794			Sep 11 03:37:37 AM UTC 24	Sep 11 03:42:33 AM UTC 24	78699205959 ps
T151	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.4054734386			Sep 11 03:37:37 AM UTC 24	Sep 11 03:42:34 AM UTC 24	496217279018 ps
T159	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3041462889			Sep 11 03:42:35 AM UTC 24	Sep 11 03:42:38 AM UTC 24	3146576415 ps
T81	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3514793407			Sep 11 03:37:38 AM UTC 24	Sep 11 03:42:52 AM UTC 24	429885928748 ps
T160	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2934613237			Sep 11 03:37:57 AM UTC 24	Sep 11 03:42:57 AM UTC 24	340845319759 ps
T161	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2167857602			Sep 11 03:38:42 AM UTC 24	Sep 11 03:42:58 AM UTC 24	499254592008 ps
T144	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.2748507500			Sep 11 03:38:12 AM UTC 24	Sep 11 03:43:03 AM UTC 24	327477632416 ps
T145	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2573727223			Sep 11 03:37:35 AM UTC 24	Sep 11 03:43:03 AM UTC 24	482631006632 ps
T162	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1511807081			Sep 11 03:43:04 AM UTC 24	Sep 11 03:43:07 AM UTC 24	290374020 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1564603747			Sep 11 03:42:59 AM UTC 24	Sep 11 03:43:08 AM UTC 24	14133925410 ps
T138	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1604814388			Sep 11 03:37:52 AM UTC 24	Sep 11 03:43:09 AM UTC 24	332845474318 ps
T185	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.238199579			Sep 11 03:43:04 AM UTC 24	Sep 11 03:43:13 AM UTC 24	6050489776 ps
T182	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2809716040			Sep 11 03:37:49 AM UTC 24	Sep 11 03:43:22 AM UTC 24	489662663287 ps
T139	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.3297648565			Sep 11 03:37:36 AM UTC 24	Sep 11 03:43:27 AM UTC 24	537756713701 ps
T146	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2994304074			Sep 11 03:37:36 AM UTC 24	Sep 11 03:43:47 AM UTC 24	554457445187 ps
T186	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.310419498			Sep 11 03:39:42 AM UTC 24	Sep 11 03:43:54 AM UTC 24	159920150160 ps
T171	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.1767135854			Sep 11 03:38:39 AM UTC 24	Sep 11 03:43:55 AM UTC 24	499101829932 ps
T357	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.1811271352			Sep 11 03:41:32 AM UTC 24	Sep 11 03:43:57 AM UTC 24	43934903193 ps
T358	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.1202071978			Sep 11 03:37:37 AM UTC 24	Sep 11 03:43:58 AM UTC 24	162731964622 ps
T359	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.2848303155			Sep 11 03:42:39 AM UTC 24	Sep 11 03:44:05 AM UTC 24	22698506987 ps
T360	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.710945864			Sep 11 03:37:37 AM UTC 24	Sep 11 03:44:16 AM UTC 24	163562757240 ps
T361	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.826209127			Sep 11 03:43:55 AM UTC 24	Sep 11 03:44:17 AM UTC 24	4317036275 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.532363066			Sep 11 03:44:06 AM UTC 24	Sep 11 03:44:20 AM UTC 24	12261466235 ps
T362	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1479848437			Sep 11 03:44:18 AM UTC 24	Sep 11 03:44:22 AM UTC 24	496733301 ps
T363	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1238600857			Sep 11 03:44:21 AM UTC 24	Sep 11 03:44:28 AM UTC 24	5977780847 ps
T364	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.269229781			Sep 11 03:43:59 AM UTC 24	Sep 11 03:44:33 AM UTC 24	32734910352 ps
T163	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.1989002281			Sep 11 03:37:49 AM UTC 24	Sep 11 03:44:33 AM UTC 24	167134884834 ps
T140	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3550242292			Sep 11 03:43:10 AM UTC 24	Sep 11 03:44:51 AM UTC 24	163050916752 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2235482324			Sep 11 03:37:54 AM UTC 24	Sep 11 03:45:01 AM UTC 24	94830831568 ps
T167	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.3008439595			Sep 11 03:37:25 AM UTC 24	Sep 11 03:45:01 AM UTC 24	161449640720 ps
T141	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.3461498560			Sep 11 03:43:08 AM UTC 24	Sep 11 03:45:20 AM UTC 24	486733233960 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1556981989			Sep 11 03:37:37 AM UTC 24	Sep 11 03:45:21 AM UTC 24	93095710337 ps
T216	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.2064836197			Sep 11 03:42:30 AM UTC 24	Sep 11 03:45:23 AM UTC 24	161483968684 ps
T172	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1649025527			Sep 11 03:42:22 AM UTC 24	Sep 11 03:45:30 AM UTC 24	201386665095 ps
T365	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1524809227			Sep 11 03:45:22 AM UTC 24	Sep 11 03:45:30 AM UTC 24	3340354606 ps
T173	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2472457868			Sep 11 03:37:37 AM UTC 24	Sep 11 03:45:34 AM UTC 24	636370669689 ps
T366	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1093853350			Sep 11 03:37:51 AM UTC 24	Sep 11 03:45:41 AM UTC 24	389418193188 ps
T147	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2021315775			Sep 11 03:41:17 AM UTC 24	Sep 11 03:45:43 AM UTC 24	362871636288 ps
T168	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1399884688			Sep 11 03:38:44 AM UTC 24	Sep 11 03:45:44 AM UTC 24	513737571800 ps
T367	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1523069140			Sep 11 03:45:42 AM UTC 24	Sep 11 03:45:44 AM UTC 24	300596766 ps
T164	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1471206682			Sep 11 03:37:36 AM UTC 24	Sep 11 03:45:46 AM UTC 24	186773477236 ps
T148	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.4021638718			Sep 11 03:45:02 AM UTC 24	Sep 11 03:45:48 AM UTC 24	208046577562 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2406526991			Sep 11 03:45:31 AM UTC 24	Sep 11 03:45:48 AM UTC 24	5827392892 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1398311030			Sep 11 03:45:44 AM UTC 24	Sep 11 03:46:10 AM UTC 24	5939604067 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1714079607			Sep 11 03:42:09 AM UTC 24	Sep 11 03:46:15 AM UTC 24	327635068672 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.2537740432			Sep 11 03:45:24 AM UTC 24	Sep 11 03:46:27 AM UTC 24	38456601549 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.756644895			Sep 11 03:40:16 AM UTC 24	Sep 11 03:46:33 AM UTC 24	564071985263 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.2581159985			Sep 11 03:44:17 AM UTC 24	Sep 11 03:46:35 AM UTC 24	204291575969 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2602030501			Sep 11 03:37:47 AM UTC 24	Sep 11 03:46:38 AM UTC 24	169429945642 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.4002848605			Sep 11 03:37:37 AM UTC 24	Sep 11 03:46:39 AM UTC 24	171035896807 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.579646630			Sep 11 03:46:34 AM UTC 24	Sep 11 03:46:43 AM UTC 24	3722182968 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2379484474			Sep 11 03:44:23 AM UTC 24	Sep 11 03:46:45 AM UTC 24	492471184756 ps
T179	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.3240613095			Sep 11 03:46:46 AM UTC 24	Sep 11 03:46:48 AM UTC 24	550963498 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.764232024			Sep 11 03:46:40 AM UTC 24	Sep 11 03:46:53 AM UTC 24	5515763749 ps
T180	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.1696527710			Sep 11 03:46:49 AM UTC 24	Sep 11 03:46:57 AM UTC 24	5646243368 ps
T181	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.3708627980			Sep 11 03:38:30 AM UTC 24	Sep 11 03:47:14 AM UTC 24	493949033874 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.4190378083			Sep 11 03:37:37 AM UTC 24	Sep 11 03:47:15 AM UTC 24	299018334322 ps
T142	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.360656955			Sep 11 03:42:07 AM UTC 24	Sep 11 03:47:22 AM UTC 24	331060358571 ps
T368	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.2441230275			Sep 11 03:46:36 AM UTC 24	Sep 11 03:47:43 AM UTC 24	32861452073 ps
T165	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3820358033			Sep 11 03:46:16 AM UTC 24	Sep 11 03:47:47 AM UTC 24	549645386032 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.2689428575			Sep 11 03:37:41 AM UTC 24	Sep 11 03:47:50 AM UTC 24	112815547414 ps
T188	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.1318688591			Sep 11 03:39:27 AM UTC 24	Sep 11 03:47:56 AM UTC 24	489453004054 ps
T192	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1834324108			Sep 11 03:38:20 AM UTC 24	Sep 11 03:48:00 AM UTC 24	89603679974 ps
T166	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.949576963			Sep 11 03:38:22 AM UTC 24	Sep 11 03:48:05 AM UTC 24	173614131267 ps
T369	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.2500401061			Sep 11 03:47:57 AM UTC 24	Sep 11 03:48:13 AM UTC 24	3506248295 ps
T370	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1425728908			Sep 11 03:48:01 AM UTC 24	Sep 11 03:48:15 AM UTC 24	28501729445 ps
T371	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2228494848			Sep 11 03:48:14 AM UTC 24	Sep 11 03:48:22 AM UTC 24	1371792590 ps
T372	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2216407470			Sep 11 03:48:23 AM UTC 24	Sep 11 03:48:25 AM UTC 24	523604843 ps
T206	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3129541868			Sep 11 03:43:23 AM UTC 24	Sep 11 03:48:28 AM UTC 24	521053109140 ps
T373	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.146199326			Sep 11 03:48:26 AM UTC 24	Sep 11 03:48:34 AM UTC 24	5525870052 ps
T228	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1016174558			Sep 11 03:45:49 AM UTC 24	Sep 11 03:48:34 AM UTC 24	165821160832 ps
T210	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.1275243305			Sep 11 03:37:37 AM UTC 24	Sep 11 03:48:44 AM UTC 24	551123514930 ps
T73	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1652748249			Sep 11 03:39:08 AM UTC 24	Sep 11 03:49:31 AM UTC 24	89884149964 ps
T211	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.379085786			Sep 11 03:42:10 AM UTC 24	Sep 11 03:49:47 AM UTC 24	376388136804 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3426642655			Sep 11 03:42:59 AM UTC 24	Sep 11 03:49:47 AM UTC 24	262501240755 ps
T374	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.4149533201			Sep 11 03:37:49 AM UTC 24	Sep 11 03:49:51 AM UTC 24	324681442024 ps
T74	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.183062073			Sep 11 03:41:37 AM UTC 24	Sep 11 03:49:57 AM UTC 24	99484177094 ps
T375	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.4076940054			Sep 11 03:49:58 AM UTC 24	Sep 11 03:50:05 AM UTC 24	4807731342 ps
T239	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.3271590442			Sep 11 03:47:47 AM UTC 24	Sep 11 03:50:19 AM UTC 24	165827141791 ps
T376	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.855981637			Sep 11 03:50:06 AM UTC 24	Sep 11 03:50:30 AM UTC 24	31218469721 ps
T174	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3949155783			Sep 11 03:46:54 AM UTC 24	Sep 11 03:50:31 AM UTC 24	327017080075 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.618013792			Sep 11 03:50:31 AM UTC 24	Sep 11 03:50:40 AM UTC 24	1622276415 ps
T377	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2348623447			Sep 11 03:50:41 AM UTC 24	Sep 11 03:50:45 AM UTC 24	490704067 ps
T378	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3812768051			Sep 11 03:47:16 AM UTC 24	Sep 11 03:50:46 AM UTC 24	325869468993 ps
T199	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.713017339			Sep 11 03:37:43 AM UTC 24	Sep 11 03:50:48 AM UTC 24	307864083094 ps
T379	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1615653412			Sep 11 03:46:11 AM UTC 24	Sep 11 03:50:50 AM UTC 24	205237093170 ps
T380	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2760927154			Sep 11 03:50:45 AM UTC 24	Sep 11 03:50:56 AM UTC 24	5896352722 ps
T381	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1177946063			Sep 11 03:48:34 AM UTC 24	Sep 11 03:50:57 AM UTC 24	167057138508 ps
T223	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2603395011			Sep 11 03:37:37 AM UTC 24	Sep 11 03:51:20 AM UTC 24	505000114740 ps
T382	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2341401736			Sep 11 03:44:29 AM UTC 24	Sep 11 03:51:29 AM UTC 24	163253524958 ps
T347	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.1357325298			Sep 11 03:42:54 AM UTC 24	Sep 11 03:52:03 AM UTC 24	115932876811 ps
T229	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.1942174266			Sep 11 03:43:48 AM UTC 24	Sep 11 03:52:11 AM UTC 24	170905405147 ps
T383	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3651284905			Sep 11 03:52:12 AM UTC 24	Sep 11 03:52:19 AM UTC 24	4738591629 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.4079331647			Sep 11 03:37:37 AM UTC 24	Sep 11 03:52:32 AM UTC 24	542680862962 ps
T384	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.2017831499			Sep 11 03:37:35 AM UTC 24	Sep 11 03:52:42 AM UTC 24	333106054085 ps
T385	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3605815332			Sep 11 03:41:52 AM UTC 24	Sep 11 03:52:47 AM UTC 24	313010269135 ps
T169	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3280417132			Sep 11 03:45:47 AM UTC 24	Sep 11 03:52:54 AM UTC 24	496967340864 ps
T386	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3169524712			Sep 11 03:52:54 AM UTC 24	Sep 11 03:52:57 AM UTC 24	305732314 ps
T250	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2480552880			Sep 11 03:52:43 AM UTC 24	Sep 11 03:53:00 AM UTC 24	12313185792 ps
T233	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.3148599072			Sep 11 03:43:54 AM UTC 24	Sep 11 03:53:06 AM UTC 24	163412793160 ps
T209	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2758836883			Sep 11 03:48:35 AM UTC 24	Sep 11 03:53:17 AM UTC 24	327996180664 ps
T231	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.210900697			Sep 11 03:37:38 AM UTC 24	Sep 11 03:53:22 AM UTC 24	359877146675 ps
T387	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2229582315			Sep 11 03:52:57 AM UTC 24	Sep 11 03:53:24 AM UTC 24	5635829869 ps
T249	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.1611589182			Sep 11 03:44:52 AM UTC 24	Sep 11 03:53:29 AM UTC 24	404045587759 ps
T322	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.2458264886			Sep 11 03:50:47 AM UTC 24	Sep 11 03:53:33 AM UTC 24	163813369798 ps
T388	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3875020196			Sep 11 03:38:00 AM UTC 24	Sep 11 03:53:40 AM UTC 24	324810346133 ps
T389	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3484696622			Sep 11 03:52:20 AM UTC 24	Sep 11 03:53:48 AM UTC 24	41415505305 ps
T390	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.1835759180			Sep 11 03:53:49 AM UTC 24	Sep 11 03:53:56 AM UTC 24	4683514314 ps
T265	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.4234396627			Sep 11 03:47:15 AM UTC 24	Sep 11 03:54:06 AM UTC 24	162531200259 ps
T240	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1955677177			Sep 11 03:46:28 AM UTC 24	Sep 11 03:54:43 AM UTC 24	166339357819 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3443891976			Sep 11 03:50:32 AM UTC 24	Sep 11 03:54:55 AM UTC 24	337082080207 ps
T391	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3851923668			Sep 11 03:54:43 AM UTC 24	Sep 11 03:54:56 AM UTC 24	5997356773 ps
T392	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3949931681			Sep 11 03:54:57 AM UTC 24	Sep 11 03:55:00 AM UTC 24	374718446 ps
T170	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.1687942227			Sep 11 03:49:48 AM UTC 24	Sep 11 03:55:09 AM UTC 24	353381532315 ps
T393	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3894548772			Sep 11 03:55:01 AM UTC 24	Sep 11 03:55:17 AM UTC 24	5706374597 ps
T394	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.494542274			Sep 11 03:53:56 AM UTC 24	Sep 11 03:55:39 AM UTC 24	46058308276 ps
T395	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1907395052			Sep 11 03:45:49 AM UTC 24	Sep 11 03:55:46 AM UTC 24	167825260738 ps
T225	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3846004986			Sep 11 03:50:50 AM UTC 24	Sep 11 03:55:47 AM UTC 24	159208130729 ps
T187	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.417646418			Sep 11 03:53:34 AM UTC 24	Sep 11 03:56:01 AM UTC 24	548957602569 ps
T396	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2973132786			Sep 11 03:38:44 AM UTC 24	Sep 11 03:56:19 AM UTC 24	401128325211 ps
T397	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.3779937522			Sep 11 03:45:45 AM UTC 24	Sep 11 03:56:31 AM UTC 24	479748221140 ps
T398	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1645758104			Sep 11 03:50:57 AM UTC 24	Sep 11 03:56:35 AM UTC 24	326359533014 ps
T207	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3619411215			Sep 11 03:53:41 AM UTC 24	Sep 11 03:56:47 AM UTC 24	487290819412 ps
T399	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3675272067			Sep 11 03:56:35 AM UTC 24	Sep 11 03:56:56 AM UTC 24	4409098576 ps
T252	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.412530897			Sep 11 03:47:51 AM UTC 24	Sep 11 03:57:00 AM UTC 24	336759329616 ps
T400	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2174931826			Sep 11 03:48:45 AM UTC 24	Sep 11 03:57:10 AM UTC 24	164163993761 ps
T267	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1000534856			Sep 11 03:57:01 AM UTC 24	Sep 11 03:57:13 AM UTC 24	15571007358 ps
T234	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.1093265196			Sep 11 03:47:22 AM UTC 24	Sep 11 03:57:13 AM UTC 24	372565055621 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.442064364			Sep 11 03:52:04 AM UTC 24	Sep 11 03:57:14 AM UTC 24	561534211023 ps
T401	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.4225689259			Sep 11 03:56:47 AM UTC 24	Sep 11 03:57:16 AM UTC 24	38932415884 ps
T402	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.1610286428			Sep 11 03:57:14 AM UTC 24	Sep 11 03:57:16 AM UTC 24	468492798 ps
T403	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1825507517			Sep 11 03:57:14 AM UTC 24	Sep 11 03:57:22 AM UTC 24	5817224920 ps
T404	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3989354510			Sep 11 03:37:58 AM UTC 24	Sep 11 03:57:26 AM UTC 24	498167053083 ps
T405	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4030561708			Sep 11 03:53:30 AM UTC 24	Sep 11 03:57:29 AM UTC 24	576496138981 ps
T251	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.233335701			Sep 11 03:38:30 AM UTC 24	Sep 11 03:57:47 AM UTC 24	489313555219 ps
T275	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2742459112			Sep 11 03:50:57 AM UTC 24	Sep 11 03:57:48 AM UTC 24	170732690851 ps
T194	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.4010751981			Sep 11 03:43:59 AM UTC 24	Sep 11 03:57:51 AM UTC 24	143877206041 ps
T334	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.4167578725			Sep 11 03:49:32 AM UTC 24	Sep 11 03:57:53 AM UTC 24	195231462843 ps
T406	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.303746326			Sep 11 03:57:51 AM UTC 24	Sep 11 03:57:58 AM UTC 24	3896729766 ps
T407	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.775892403			Sep 11 03:57:53 AM UTC 24	Sep 11 03:58:17 AM UTC 24	21603299197 ps
T214	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.843134518			Sep 11 03:39:22 AM UTC 24	Sep 11 03:58:28 AM UTC 24	302339330470 ps
T260	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1567812690			Sep 11 03:58:18 AM UTC 24	Sep 11 03:58:35 AM UTC 24	34132876553 ps
T193	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3588792186			Sep 11 03:46:44 AM UTC 24	Sep 11 03:58:38 AM UTC 24	272205667408 ps
T408	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1897043431			Sep 11 03:58:36 AM UTC 24	Sep 11 03:58:38 AM UTC 24	411414455 ps
T409	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3135915895			Sep 11 03:46:58 AM UTC 24	Sep 11 03:58:45 AM UTC 24	499919269805 ps
T410	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1245350248			Sep 11 03:58:39 AM UTC 24	Sep 11 03:58:48 AM UTC 24	5912375076 ps
T411	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2245535317			Sep 11 03:53:06 AM UTC 24	Sep 11 03:58:57 AM UTC 24	169045073710 ps
T412	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.499465290			Sep 11 03:39:33 AM UTC 24	Sep 11 03:59:20 AM UTC 24	331164277335 ps
T175	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.782934356			Sep 11 03:45:44 AM UTC 24	Sep 11 03:59:33 AM UTC 24	328496930176 ps
T255	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.2975354698			Sep 11 03:57:48 AM UTC 24	Sep 11 03:59:38 AM UTC 24	161255473860 ps
T413	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2104258892			Sep 11 03:44:34 AM UTC 24	Sep 11 03:59:41 AM UTC 24	325539505461 ps
T224	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.2955289033			Sep 11 03:41:44 AM UTC 24	Sep 11 03:59:42 AM UTC 24	274196302441 ps
T414	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3772844113			Sep 11 03:55:47 AM UTC 24	Sep 11 03:59:48 AM UTC 24	321978871544 ps
T153	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.4115303337			Sep 11 03:51:30 AM UTC 24	Sep 11 03:59:49 AM UTC 24	488996060850 ps
T415	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3417541474			Sep 11 03:59:43 AM UTC 24	Sep 11 03:59:49 AM UTC 24	5105509372 ps
T218	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1414914630			Sep 11 03:59:50 AM UTC 24	Sep 11 04:00:05 AM UTC 24	33404909922 ps
T198	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.576372615			Sep 11 03:45:31 AM UTC 24	Sep 11 04:00:09 AM UTC 24	137660045680 ps
T154	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.197368649			Sep 11 03:41:48 AM UTC 24	Sep 11 04:00:10 AM UTC 24	328354610358 ps
T416	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.699814212			Sep 11 04:00:10 AM UTC 24	Sep 11 04:00:13 AM UTC 24	505218996 ps
T417	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.880234367			Sep 11 03:56:02 AM UTC 24	Sep 11 04:00:15 AM UTC 24	610763671701 ps
T418	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2488935061			Sep 11 04:00:11 AM UTC 24	Sep 11 04:00:18 AM UTC 24	5685957123 ps
T222	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2128820263			Sep 11 03:44:34 AM UTC 24	Sep 11 04:00:19 AM UTC 24	325638750153 ps
T261	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.3863865394			Sep 11 03:37:49 AM UTC 24	Sep 11 04:00:22 AM UTC 24	549855044953 ps
T419	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1596316959			Sep 11 03:59:49 AM UTC 24	Sep 11 04:00:23 AM UTC 24	20916686514 ps
T420	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.3521484109			Sep 11 03:50:19 AM UTC 24	Sep 11 04:00:27 AM UTC 24	70767884700 ps
T421	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.933868653			Sep 11 03:40:22 AM UTC 24	Sep 11 04:00:27 AM UTC 24	390869562400 ps
T422	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1239964846			Sep 11 03:53:24 AM UTC 24	Sep 11 04:00:36 AM UTC 24	166463234541 ps
T423	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1511116972			Sep 11 04:00:37 AM UTC 24	Sep 11 04:00:43 AM UTC 24	3721443858 ps
T232	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2179037475			Sep 11 03:55:40 AM UTC 24	Sep 11 04:00:45 AM UTC 24	489346278693 ps
T424	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3778726310			Sep 11 03:45:02 AM UTC 24	Sep 11 04:00:46 AM UTC 24	622475657764 ps
T425	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.2757553508			Sep 11 04:00:44 AM UTC 24	Sep 11 04:01:05 AM UTC 24	34332202601 ps
T190	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.2801903055			Sep 11 03:46:39 AM UTC 24	Sep 11 04:01:13 AM UTC 24	112575573200 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1979627327			Sep 11 04:00:47 AM UTC 24	Sep 11 04:01:15 AM UTC 24	14014512180 ps
T426	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1634707914			Sep 11 04:01:14 AM UTC 24	Sep 11 04:01:16 AM UTC 24	426207650 ps
T427	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4163410768			Sep 11 03:37:37 AM UTC 24	Sep 11 04:01:27 AM UTC 24	589319050141 ps
T155	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1522619344			Sep 11 03:57:48 AM UTC 24	Sep 11 04:01:28 AM UTC 24	368945201758 ps
T428	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.3957878603			Sep 11 04:01:16 AM UTC 24	Sep 11 04:01:32 AM UTC 24	5630272589 ps
T429	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.923821414			Sep 11 03:43:28 AM UTC 24	Sep 11 04:01:35 AM UTC 24	403825638720 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.925998974			Sep 11 03:54:55 AM UTC 24	Sep 11 04:01:55 AM UTC 24	168413607113 ps
T430	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.438228169			Sep 11 03:43:09 AM UTC 24	Sep 11 04:01:58 AM UTC 24	490245561838 ps
T230	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.646558051			Sep 11 03:40:53 AM UTC 24	Sep 11 04:02:05 AM UTC 24	503152197146 ps
T431	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4219563403			Sep 11 04:00:23 AM UTC 24	Sep 11 04:02:22 AM UTC 24	209715871455 ps
T432	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2438677749			Sep 11 04:02:23 AM UTC 24	Sep 11 04:02:26 AM UTC 24	5219076954 ps
T433	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.2682088470			Sep 11 03:57:17 AM UTC 24	Sep 11 04:02:40 AM UTC 24	323541191157 ps
T434	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.737306946			Sep 11 03:50:49 AM UTC 24	Sep 11 04:02:45 AM UTC 24	491798838026 ps
T98	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2334798421			Sep 11 04:02:46 AM UTC 24	Sep 11 04:02:51 AM UTC 24	1226448559 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.2842706972			Sep 11 03:45:35 AM UTC 24	Sep 11 04:03:06 AM UTC 24	294484085438 ps
T104	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3934143100			Sep 11 03:59:38 AM UTC 24	Sep 11 04:03:08 AM UTC 24	338248648335 ps
T105	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.1338317464			Sep 11 04:03:07 AM UTC 24	Sep 11 04:03:10 AM UTC 24	286536047 ps
T106	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.2130770796			Sep 11 03:57:15 AM UTC 24	Sep 11 04:03:18 AM UTC 24	494227757212 ps
T107	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.300693084			Sep 11 04:03:09 AM UTC 24	Sep 11 04:03:18 AM UTC 24	5917799842 ps
T108	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.540669014			Sep 11 03:58:57 AM UTC 24	Sep 11 04:03:20 AM UTC 24	161288229435 ps
T109	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.369791985			Sep 11 04:01:28 AM UTC 24	Sep 11 04:03:36 AM UTC 24	485111708453 ps
T110	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3575502919			Sep 11 03:43:14 AM UTC 24	Sep 11 04:03:47 AM UTC 24	494221897660 ps
T111	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.1678107097			Sep 11 04:02:06 AM UTC 24	Sep 11 04:03:54 AM UTC 24	162129536774 ps
T237	/workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.31919194			Sep 11 04:00:07 AM UTC 24	Sep 11 04:03:57 AM UTC 24	520631236495 ps