Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21830

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3196

1

T12

6

T13

5

T17

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19158

1

T1

20

T4

10

T5

20

auto[1]

5868

1

T9

5

T13

5

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T40	1		T205	17		-	-
values[0]	43	1			T145	10		T206	13		T207	10
values[1]	627	1			T50	2		T151	1		T81	11
values[2]	687	1			T12	1		T13	5		T144	5
values[3]	560	1			T12	5		T160	1		T144	12
values[4]	3258	1			T15	26		T17	14		T19	1
values[5]	420	1			T70	33		T208	14		T151	1
values[6]	478	1			T7	4		T14	1		T138	11
values[7]	528	1			T16	4		T52	25		T146	1
values[8]	850	1			T137	2		T70	10		T145	4
values[9]	1326	1			T9	5		T18	2		T50	28
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	884	1			T12	1		T13	5		T50	2
values[1]	645	1			T151	1		T138	28		T171	1
values[2]	613	1			T12	5		T160	1		T144	17
values[3]	3065	1			T15	26		T17	14		T19	1
values[4]	475	1			T151	1		T38	14		T43	2
values[5]	586	1			T7	4		T208	14		T138	11
values[6]	520	1			T14	1		T16	4		T52	25
values[7]	754	1			T137	2		T145	4		T139	32
values[8]	1022	1			T9	5		T18	2		T50	28
values[9]	217	1			T151	1		T39	7		T209	14
minimum	16245	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T50	1		T145	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T13	4		T81	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T171	1		T141	1		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	1		T138	12		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T144	3		T63	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	4		T160	1		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1681	1			T15	3		T19	1		T51	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	1		T70	20		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T43	1		T210	11		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T151	1		T38	14		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	3		T208	1		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T26	3		T71	14		T211	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	1		T16	3		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T70	6		T146	12		T164	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T137	2		T145	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	16		T171	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T9	3		T61	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T18	1		T50	16		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T39	5		T170	1		T212	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T151	1		T209	1		T213	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16140	1			T1	20		T4	10		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	1		T145	9		T147	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	1		T81	8		T62	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T165	3		T214	14		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T138	16		T148	16		T215	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T144	2		T216	8		T217	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T144	2		T166	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T15	23		T97	3		T81	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	13		T70	13		T142	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T169	5		T209	8		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T219	14		T220	9		T221	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T208	13		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T26	1		T71	13		T222	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T52	12		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T70	4		T207	2		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T145	3		T165	7		T225	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T139	16		T171	5		T140	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	2		T61	1		T223	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T18	1		T50	12		T53	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T39	2		T170	1		T212	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T209	13		T226	11		T227	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	1		T12	3		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T40	1		T205	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T145	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T206	13		T207	5		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	1		T173	1		T228	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T151	1		T81	3		T62	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T144	3		T147	6		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T13	4		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T171	1		T167	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	4		T160	1		T144	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1747	1			T15	3		T19	1		T51	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T17	1		T146	10		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T208	1		T25	1		T210	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T70	20		T151	1		T38	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	3		T14	1		T138	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T146	12		T43	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	3		T52	13		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T71	14		T188	1		T223	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T137	2		T145	1		T139	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T70	6		T139	16		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T9	3		T61	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T18	1		T50	16		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T205	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T145	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T207	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T50	1		T229	10		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T81	8		T62	2		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T144	2		T147	2		T165	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T138	16		T148	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T214	14		T153	1		T230	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T144	2		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T15	23		T97	3		T81	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T17	13		T166	16		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T208	13		T169	5		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T70	13		T142	6		T170	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	1		T138	6		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T26	1		T222	2		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	1		T52	12		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T71	13		T224	13		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T145	3		T165	7		T233	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T70	4		T139	16		T171	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T9	2		T61	1		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T18	1		T50	12		T53	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	2		T145	10		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	1		T13	4		T81	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T171	1		T141	1		T165	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T151	1		T138	17		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T144	3		T63	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	3		T160	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T15	26		T19	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	14		T70	14		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	1		T210	1		T169	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T151	1		T38	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	3		T208	14		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T26	3		T71	14		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	1		T16	3		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T70	5		T146	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T137	1		T145	4		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	17		T171	6		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	4		T61	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T18	2		T50	13		T53	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T39	3		T170	2		T212	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T151	1		T209	14		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16245	1			T1	20		T4	10		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T147	5		T228	17		T229	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T81	2		T62	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T165	12		T210	4		T234	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T138	11		T148	13		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T144	2		T216	9		T168	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	2		T144	9		T173	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T51	14		T64	18		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T70	19		T146	9		T38	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T210	10		T218	1		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T38	13		T165	8		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	1		T138	4		T173	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T26	1		T71	13		T211	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	1		T52	12		T139	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T70	5		T146	11		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	1		T168	8		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T139	15		T237	10		T238	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	1		T61	1		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	15		T70	7		T240	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T39	4		T212	18		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T213	11		T226	13		T227	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T40	1		T205	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T145	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T206	1		T207	6		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	2		T173	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T151	1		T81	9		T62	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T144	3		T147	3		T165	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T13	4		T138	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T171	1		T167	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	3		T160	1		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T15	26		T19	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T17	14		T146	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T208	14		T25	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T70	14		T151	1		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	3		T14	1		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T146	1		T43	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	3		T52	13		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T71	14		T188	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T137	1		T145	4		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T70	5		T139	17		T171	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T9	4		T61	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T18	2		T50	13		T53	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T206	12		T207	4		T242	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T228	17		T229	8		T231	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T81	2		T62	2		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T144	2		T147	5		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	1		T138	11		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T230	14		T243	9		T244	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	2		T144	9		T173	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T51	14		T64	18		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T146	9		T38	12		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T210	10		T245	8		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T70	19		T38	13		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	1		T138	4		T173	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T146	11		T26	1		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	1		T52	12		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T71	13		T223	14		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T137	1		T139	7		T168	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T70	5		T139	15		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T9	1		T61	1		T39	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T50	15		T70	7		T240	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21780

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3246

1

T7

4

T9

5

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19363

1

T1

20

T4

10

T5

20

auto[1]

5663

1

T9

5

T13

5

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	48	1			T138	28		T246	1		T247	19
values[0]	16	1			T32	4		T248	12		-	-
values[1]	708	1			T208	14		T63	1		T147	22
values[2]	625	1			T70	33		T139	8		T146	1
values[3]	573	1			T12	1		T13	5		T14	1
values[4]	626	1			T18	2		T137	2		T151	1
values[5]	696	1			T151	1		T160	1		T145	10
values[6]	681	1			T9	5		T70	14		T160	1
values[7]	706	1			T7	4		T12	5		T50	28
values[8]	2865	1			T15	26		T17	14		T19	1
values[9]	1251	1			T70	10		T151	1		T144	12
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	818	1			T70	33		T208	14		T63	1
values[1]	591	1			T12	1		T140	7		T141	1
values[2]	613	1			T13	5		T14	1		T16	4
values[3]	638	1			T18	2		T137	2		T151	1
values[4]	737	1			T151	1		T160	2		T144	5
values[5]	609	1			T70	14		T171	6		T38	14
values[6]	3005	1			T7	4		T9	5		T12	5
values[7]	565	1			T17	14		T50	2		T53	13
values[8]	1040	1			T70	10		T151	1		T144	12
values[9]	147	1			T249	3		T152	29		T246	1
minimum	16263	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T70	20		T63	1		T168	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T208	1		T174	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	1		T210	19		T223	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T141	1		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T16	3		T81	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	4		T145	1		T139	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T145	1		T138	5		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T18	1		T137	2		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T151	1		T160	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T160	1		T144	3		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T70	8		T38	14		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T171	1		T250	2		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1674	1			T12	4		T15	3		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	3		T9	3		T50	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T17	1		T50	1		T61	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T53	1		T216	10		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T151	1		T144	10		T252	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T70	6		T138	12		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T249	3		T253	1		T215	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T152	17		T246	1		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T152	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T70	13		T229	10		T47	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T208	13		T170	4		T187	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T140	6		T209	13		T225	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T147	10		T75	6		T187	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	1		T81	8		T145	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	1		T145	3		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T145	9		T138	6		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	1		T62	2		T165	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T148	16		T230	6		T111	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T144	2		T142	6		T166	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T70	6		T41	6		T71	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T171	5		T214	14		T255	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T12	1		T15	23		T52	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	1		T9	2		T50	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	13		T50	1		T61	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T53	12		T216	8		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	2		T252	7		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T70	4		T138	16		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T253	1		T215	3		T256	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T152	12		T254	15		T257	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T152	19		-	-		-	-