Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21665

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3361

1

T7

4

T12

5

T17

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18815

1

T1

20

T4

10

T5

20

auto[1]

6211

1

T7

4

T12

1

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	660	1			T14	5		T19	1		T53	13
values[0]	18	1			T232	15		T320	1		T321	2
values[1]	606	1			T9	5		T16	4		T17	14
values[2]	2995	1			T12	5		T15	26		T51	15
values[3]	891	1			T14	1		T61	4		T70	33
values[4]	510	1			T52	25		T160	1		T140	7
values[5]	602	1			T62	7		T139	8		T146	1
values[6]	730	1			T151	1		T141	1		T168	13
values[7]	668	1			T12	1		T13	5		T137	12
values[8]	644	1			T7	4		T151	1		T144	5
values[9]	825	1			T18	2		T50	2		T137	2
minimum	15877	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	604	1			T16	4		T17	14		T171	15
values[1]	2992	1			T12	5		T14	1		T15	26
values[2]	887	1			T52	25		T61	4		T70	33
values[3]	537	1			T160	1		T140	7		T167	1
values[4]	528	1			T62	7		T139	8		T146	1
values[5]	738	1			T137	12		T151	1		T211	11
values[6]	750	1			T12	1		T13	5		T70	14
values[7]	483	1			T7	4		T137	2		T144	5
values[8]	979	1			T18	2		T50	2		T53	13
values[9]	93	1			T19	1		T70	10		T160	1
minimum	16435	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	3		T174	1		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T171	1		T39	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1541	1			T14	1		T15	3		T51	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T12	4		T144	10		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T52	13		T81	3		T139	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T61	3		T70	20		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T167	1		T71	14		T210	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T160	1		T140	1		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T163	1		T148	14		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T62	5		T139	8		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T151	1		T211	11		T75	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T137	12		T75	1		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T12	1		T13	4		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T70	8		T151	1		T81	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T137	2		T173	12		T322	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	3		T144	3		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T18	1		T53	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T50	1		T171	1		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T19	1		T70	6		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T142	1		T169	1		T233	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16196	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T50	16		T151	1		T216	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	1		T187	1		T308	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	13		T171	14		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T15	23		T97	3		T161	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T144	2		T145	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T52	12		T81	8		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	1		T70	13		T223	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T71	13		T231	9		T47	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T140	6		T209	13		T170	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T163	12		T148	16		T207	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T62	2		T26	1		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T75	6		T169	3		T47	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T237	8		T215	3		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T171	5		T265	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T70	6		T81	14		T138	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T187	1		T28	2		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	1		T144	2		T166	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T18	1		T53	12		T208	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T50	1		T165	3		T225	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T70	4		T323	12		T324	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T142	6		T169	5		T233	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T9	2		T12	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T50	12		T216	8		T232	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	454	1			T14	5		T19	1		T53	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T43	1		T233	4		T255	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T320	1		T321	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	3		T16	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	1		T50	16		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T15	3		T51	15		T64	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	4		T144	10		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	1		T81	3		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T61	3		T70	20		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T52	13		T41	1		T71	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T160	1		T140	1		T38	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T163	1		T167	1		T148	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T62	5		T139	8		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T151	1		T165	9		T75	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T141	1		T168	13		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T13	4		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	12		T70	8		T81	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T173	12		T322	1		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	3		T151	1		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T18	1		T137	2		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T50	1		T171	1		T164	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15784	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T53	12		T70	4		T145	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T233	4		T255	12		T325	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T321	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T232	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	2		T16	1		T170	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	13		T50	12		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T15	23		T97	3		T161	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T144	2		T145	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T81	8		T139	16		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T61	1		T70	13		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T52	12		T41	6		T71	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T140	6		T223	10		T209	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T163	12		T148	16		T207	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T62	2		T229	10		T232	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T75	6		T169	3		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T26	1		T237	8		T215	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	1		T171	5		T47	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T70	6		T81	14		T138	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T265	13		T187	1		T152	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	1		T144	2		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T18	1		T208	13		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	1		T142	6		T165	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	3		T174	1		T187	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T17	14		T171	15		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T14	1		T15	26		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	3		T144	3		T145	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T52	13		T81	9		T139	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T61	3		T70	14		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T167	1		T71	14		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T160	1		T140	7		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T163	13		T148	17		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T62	5		T139	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T151	1		T211	1		T75	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T137	1		T75	1		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	1		T13	4		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T70	7		T151	1		T81	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T137	1		T173	1		T322	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	3		T144	3		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T18	2		T53	13		T208	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T50	2		T171	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T19	1		T70	5		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T142	7		T169	6		T233	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16310	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T50	13		T151	1		T216	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	1		T261	10		T308	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	4		T206	12		T187	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T51	14		T64	18		T172	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	2		T144	9		T138	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T52	12		T81	2		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T61	1		T70	19		T38	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T71	13		T210	4		T231	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T326	1		T274	11		T327	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T148	13		T165	8		T207	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T62	2		T139	7		T168	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T211	10		T75	4		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	11		T215	4		T226	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T173	11		T206	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T70	7		T81	12		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T137	1		T173	11		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	1		T144	2		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T231	13		T240	7		T48	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T164	12		T38	12		T165	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T70	5		T323	10		T324	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T233	3		T234	20		T279	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T9	1		T38	1		T170	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T50	15		T216	9		T328	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	446	1			T14	5		T19	1		T53	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T43	1		T233	5		T255	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T320	1		T321	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T232	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	4		T16	3		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T17	14		T50	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T15	26		T51	1		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	3		T144	3		T145	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	1		T81	9		T139	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T61	3		T70	14		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	13		T41	7		T71	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T160	1		T140	7		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T163	13		T167	1		T148	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	5		T139	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T151	1		T165	1		T75	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T141	1		T168	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T13	4		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T137	1		T70	7		T81	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T173	1		T322	1		T265	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	3		T151	1		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T18	2		T137	1		T208	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T50	2		T171	1		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15877	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T70	5		T230	11		T263	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T233	3		T255	12		T261	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	1		T16	1		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	15		T216	9		T39	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T51	14		T64	18		T172	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	2		T144	9		T138	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T81	2		T139	15		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T61	1		T70	19		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T52	12		T71	13		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T38	13		T223	12		T326	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T148	13		T210	4		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T62	2		T139	7		T168	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T165	8		T75	4		T249	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T168	12		T26	1		T261	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T173	11		T206	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T137	11		T70	7		T81	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T173	11		T152	12		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	1		T144	2		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	1		T231	13		T240	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T164	12		T38	12		T165	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2