Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21649

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3377

1

T7

4

T9

5

T12

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18883

1

T1

20

T4

10

T5

20

auto[1]

6143

1

T7

4

T12

6

T14

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	387	1			T14	5		T68	3		T69	4
values[0]	100	1			T216	18		T232	15		T230	29
values[1]	538	1			T9	5		T16	4		T17	14
values[2]	2919	1			T12	5		T15	26		T51	15
values[3]	945	1			T14	1		T61	4		T70	33
values[4]	490	1			T52	25		T160	1		T140	7
values[5]	646	1			T62	7		T139	8		T146	1
values[6]	690	1			T151	1		T141	1		T168	13
values[7]	700	1			T12	1		T13	5		T137	12
values[8]	568	1			T7	4		T151	1		T144	5
values[9]	1166	1			T18	2		T19	1		T50	2
minimum	15877	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	786	1			T16	4		T17	14		T50	28
values[1]	2986	1			T12	5		T14	1		T15	26
values[2]	883	1			T52	25		T61	4		T81	11
values[3]	517	1			T160	1		T140	7		T167	1
values[4]	586	1			T62	7		T139	8		T146	1
values[5]	724	1			T137	12		T70	14		T151	1
values[6]	740	1			T7	4		T12	1		T13	5
values[7]	526	1			T137	2		T144	5		T146	12
values[8]	949	1			T18	2		T19	1		T50	2
values[9]	85	1			T70	10		T142	7		T169	6
minimum	16244	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	3		T50	16		T38	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	1		T151	1		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T14	1		T15	3		T51	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	4		T70	20		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T52	13		T81	3		T139	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T61	3		T141	1		T38	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T140	1		T167	1		T210	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T160	1		T71	14		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T163	1		T148	14		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T62	5		T139	8		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T137	12		T151	1		T211	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T70	8		T169	1		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T138	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	3		T13	4		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T137	2		T146	12		T173	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T144	3		T166	15		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T18	1		T53	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T19	1		T50	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T70	6		T233	4		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T142	1		T169	1		T250	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16141	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T9	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T50	12		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	13		T171	14		T216	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T15	23		T97	3		T161	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T70	13		T145	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T52	12		T81	8		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T61	1		T223	10		T153	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T140	6		T231	9		T47	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T71	13		T209	13		T170	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T163	12		T148	16		T207	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T62	2		T26	1		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T75	6		T47	6		T267	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T70	6		T169	3		T232	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T138	16		T171	5		T152	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T13	1		T81	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T28	2		T155	14		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	2		T166	16		T199	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	1		T53	12		T208	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	1		T145	1		T165	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T70	4		T233	4		T323	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T142	6		T169	5		T329	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T9	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T14	5		T68	3		T69	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T296	1		T330	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T230	15		T331	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T216	10		T232	1		T320	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T16	3		T50	16		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	3		T17	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T15	3		T51	15		T64	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	4		T145	1		T138	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	1		T81	3		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T61	3		T70	20		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T52	13		T140	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T160	1		T168	8		T38	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T163	1		T167	1		T148	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T62	5		T139	8		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T151	1		T46	1		T75	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	1		T168	13		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T137	12		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	4		T70	8		T81	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	12		T173	12		T322	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	3		T151	1		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T18	1		T53	1		T137	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	446	1			T19	1		T50	1		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15784	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T233	4		T323	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T230	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T216	8		T232	14		T178	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T16	1		T50	12		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	2		T17	13		T187	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T15	23		T97	3		T161	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T145	3		T138	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T81	8		T144	2		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T61	1		T70	13		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T52	12		T140	6		T41	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T223	10		T209	13		T170	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T163	12		T148	16		T207	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T62	2		T71	13		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T75	6		T267	1		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	1		T169	3		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	16		T171	5		T47	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T70	6		T81	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T152	19		T155	14		T238	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	1		T144	2		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T18	1		T53	12		T70	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T50	1		T145	1		T142	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	3		T50	13		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T17	14		T151	1		T171	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T14	1		T15	26		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	3		T70	14		T145	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T52	13		T81	9		T139	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T61	3		T141	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T140	7		T167	1		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T160	1		T71	14		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T163	13		T148	17		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	5		T139	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T137	1		T151	1		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T70	7		T169	4		T232	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T138	17		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	3		T13	4		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T137	1		T146	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	3		T166	17		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T18	2		T53	13		T208	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T19	1		T50	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T70	5		T233	5		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T142	7		T169	6		T250	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16238	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T9	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	1		T50	15		T38	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T216	9		T206	12		T223	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T51	14		T64	18		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	2		T70	19		T138	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T52	12		T81	2		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T61	1		T38	13		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T210	4		T231	8		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T71	13		T263	6		T326	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T148	13		T165	8		T207	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T62	2		T139	7		T168	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T137	11		T211	10		T75	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T70	7		T215	4		T226	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T138	11		T173	11		T206	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	1		T13	1		T81	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T137	1		T146	11		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T144	2		T166	14		T199	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T231	13		T240	7		T48	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T164	12		T38	12		T165	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T70	5		T233	3		T323	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T329	8		T279	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T170	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T9	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T14	5		T68	3		T69	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T296	1		T330	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T230	15		T331	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T216	9		T232	15		T320	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	3		T50	13		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	4		T17	14		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T15	26		T51	1		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	3		T145	4		T138	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T14	1		T81	9		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T61	3		T70	14		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T52	13		T140	7		T41	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T160	1		T168	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T163	13		T167	1		T148	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T62	5		T139	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T151	1		T46	1		T75	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T141	1		T168	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T137	1		T138	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	4		T70	7		T81	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T146	1		T173	1		T322	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	3		T151	1		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T18	2		T53	13		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T19	1		T50	2		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15877	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T233	3		T323	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T230	14		T331	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T216	9		T178	9		T278	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T16	1		T50	15		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	1		T187	5		T238	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T51	14		T64	18		T172	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	2		T138	4		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T81	2		T144	9		T139	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T61	1		T70	19		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T52	12		T231	8		T332	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T168	7		T38	13		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T148	13		T165	8		T210	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T62	2		T139	7		T71	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T75	4		T267	1		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T168	12		T26	1		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T137	11		T138	11		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	1		T70	7		T81	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	11		T173	11		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	1		T144	2		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T137	1		T70	5		T231	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T164	12		T38	12		T165	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2