Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21663

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3363

1

T7

4

T14

1

T18

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19225

1

T1

20

T4

10

T5

20

auto[1]

5801

1

T7

4

T12

5

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	254	1			T71	27		T165	9		T209	9
values[0]	54	1			T169	4		T209	14		T256	28
values[1]	566	1			T12	6		T17	14		T52	25
values[2]	759	1			T53	13		T171	1		T39	7
values[3]	752	1			T14	1		T16	4		T137	12
values[4]	659	1			T19	1		T144	5		T63	1
values[5]	2907	1			T7	4		T15	26		T50	28
values[6]	490	1			T70	33		T173	12		T169	1
values[7]	716	1			T151	1		T138	28		T139	1
values[8]	757	1			T13	5		T144	12		T139	40
values[9]	881	1			T9	5		T18	2		T50	2
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	647	1			T12	6		T17	14		T52	25
values[1]	790	1			T14	1		T171	1		T148	30
values[2]	700	1			T16	4		T137	12		T70	10
values[3]	2973	1			T7	4		T15	26		T19	1
values[4]	497	1			T50	28		T61	4		T151	2
values[5]	660	1			T70	33		T151	1		T139	1
values[6]	663	1			T13	5		T138	28		T139	8
values[7]	781	1			T144	12		T139	32		T146	12
values[8]	764	1			T9	5		T18	2		T50	2
values[9]	180	1			T71	27		T209	9		T187	2
minimum	16371	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	5		T17	1		T52	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T81	13		T163	1		T168	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T171	1		T148	14		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	1		T142	1		T239	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	3		T70	6		T62	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T137	12		T145	1		T138	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T15	3		T19	1		T51	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	3		T43	1		T250	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T81	3		T171	1		T223	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T50	16		T61	3		T151	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	1		T173	12		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T70	20		T139	1		T168	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	4		T188	1		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T138	12		T139	8		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T144	10		T146	12		T38	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	16		T171	1		T147	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	3		T50	1		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T18	1		T208	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T71	14		T209	1		T153	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T187	1		T266	10		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16181	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T169	1		T193	1		T183	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T17	13		T52	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T81	14		T163	12		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T148	16		T165	3		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T75	6		T152	15		T255	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	1		T70	4		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	3		T138	6		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T15	23		T97	3		T70	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	1		T252	7		T183	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T81	8		T171	14		T223	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T50	12		T61	1		T267	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T169	5		T218	1		T222	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T70	13		T265	13		T47	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	1		T207	8		T259	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	16		T166	16		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T144	2		T231	11		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T139	16		T171	5		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	2		T50	1		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T18	1		T208	13		T145	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T71	13		T209	8		T153	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T187	1		T256	1		T268	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T169	3		T193	15		T183	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T71	14		T165	9		T209	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T152	17		T157	8		T266	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T332	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T169	1		T209	1		T256	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	5		T17	1		T52	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T81	13		T163	1		T168	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T53	1		T171	1		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	5		T142	1		T75	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	3		T70	6		T62	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	1		T137	12		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T19	1		T144	3		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T250	2		T252	16		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T15	3		T51	15		T64	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	3		T50	16		T61	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T173	12		T251	1		T218	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T70	20		T169	1		T170	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T151	1		T188	1		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T138	12		T139	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	4		T144	10		T38	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T139	24		T171	1		T147	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	3		T50	1		T137	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	1		T208	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T71	13		T209	8		T230	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T152	12		T333	5		T318	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T169	3		T209	13		T256	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T17	13		T52	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T81	14		T163	12		T207	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T53	12		T165	3		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T39	2		T75	6		T152	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	1		T70	4		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	3		T138	6		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T144	2		T140	6		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T252	7		T152	19		T219	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T15	23		T97	3		T70	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	1		T50	12		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T218	1		T222	4		T237	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T70	13		T170	4		T214	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T207	8		T156	1		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	16		T265	13		T47	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	1		T144	2		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T139	16		T171	5		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	2		T50	1		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T18	1		T208	13		T145	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	4		T17	14		T52	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T81	15		T163	13		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T171	1		T148	17		T165	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T14	1		T142	1		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	3		T70	5		T62	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T137	1		T145	4		T138	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T15	26		T19	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	3		T43	1		T250	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T81	9		T171	15		T223	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T50	13		T61	3		T151	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T151	1		T173	1		T169	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T70	14		T139	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	4		T188	1		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T138	17		T139	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T144	3		T146	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	17		T171	6		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	4		T50	2		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T18	2		T208	14		T145	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T71	14		T209	9		T153	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T187	2		T266	1		T256	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16269	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T169	4		T193	16		T183	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	2		T52	12		T206	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T81	12		T168	12		T39	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	13		T165	12		T211	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T239	10		T75	4		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	1		T70	5		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T137	11		T138	4		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T51	14		T64	18		T70	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	1		T252	15		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T81	2		T223	12		T156	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	15		T61	1		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T173	11		T218	1		T261	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T70	19		T168	8		T170	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	1		T207	7		T334	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T138	11		T139	7		T166	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T144	9		T146	11		T38	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	15		T147	5		T210	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T137	1		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T216	9		T152	16		T157	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T71	13		T153	16		T310	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T266	9		T271	11		T335	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T165	2		T336	4		T310	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T205	2		T288	15		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T71	14		T165	1		T209	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T152	13		T157	1		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T332	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T169	4		T209	14		T256	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	4		T17	14		T52	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T81	15		T163	13		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T53	13		T171	1		T165	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T39	3		T142	1		T75	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	3		T70	5		T62	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	1		T137	1		T145	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T19	1		T144	3		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T250	2		T252	8		T152	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T15	26		T51	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	3		T50	13		T61	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T173	1		T251	1		T218	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T70	14		T169	1		T170	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T151	1		T188	1		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T138	17		T139	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	4		T144	3		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	18		T171	6		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T9	4		T50	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T18	2		T208	14		T145	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T71	13		T165	8		T230	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T152	16		T157	7		T266	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T332	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T256	12		T189	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	2		T52	12		T165	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T81	12		T168	12		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T165	12		T206	12		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	4		T75	4		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T16	1		T70	5		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T137	11		T138	4		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T144	2		T168	7		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T252	15		T152	12		T213	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T51	14		T64	18		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	1		T50	15		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T173	11		T218	1		T261	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T70	19		T170	1		T230	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T207	7		T261	3		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T138	11		T168	8		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T144	9		T38	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	22		T147	5		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T137	1		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T216	9		T215	4		T226	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2