Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21517

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3509

1

T18

2

T50

28

T61

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18996

1

T1

20

T4

10

T5

20

auto[1]

6030

1

T9

5

T12

5

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	175	1			T81	11		T171	1		T251	2
values[0]	14	1			T141	1		T207	3		T318	10
values[1]	647	1			T18	2		T137	12		T70	14
values[2]	693	1			T50	2		T208	14		T206	13
values[3]	640	1			T16	4		T151	2		T146	10
values[4]	693	1			T70	33		T160	1		T140	7
values[5]	619	1			T9	5		T14	1		T50	28
values[6]	766	1			T7	4		T61	4		T138	28
values[7]	690	1			T13	5		T17	14		T53	13
values[8]	602	1			T12	5		T52	25		T160	1
values[9]	3256	1			T12	1		T15	26		T19	1
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T18	2		T137	12		T70	14
values[1]	587	1			T16	4		T50	2		T151	2
values[2]	692	1			T70	33		T146	10		T216	18
values[3]	677	1			T160	1		T140	7		T173	1
values[4]	623	1			T7	4		T9	5		T14	1
values[5]	817	1			T13	5		T61	4		T145	10
values[6]	2915	1			T12	5		T15	26		T17	14
values[7]	555	1			T52	25		T81	27		T144	5
values[8]	903	1			T12	1		T19	1		T70	10
values[9]	115	1			T166	31		T239	11		T251	1
minimum	16469	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T208	1		T141	1		T39	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T18	1		T137	12		T70	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	3		T50	1		T151	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	14		T43	1		T210	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T216	10		T147	6		T164	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T70	20		T146	10		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T160	1		T174	1		T75	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T140	1		T173	1		T211	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	3		T9	3		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	16		T151	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	4		T139	17		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T61	3		T145	1		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T12	4		T15	3		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	2		T171	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T52	13		T81	13		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T146	1		T38	2		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T19	1		T70	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T146	12		T171	1		T168	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T106	1		T238	5		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T166	15		T239	11		T251	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16212	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T141	1		T148	14		T152	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T208	13		T39	2		T222	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T18	1		T70	6		T224	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	1		T50	1		T252	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T209	8		T240	8		T170	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T216	8		T147	2		T270	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T70	13		T207	5		T232	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T75	6		T214	14		T153	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T140	6		T233	4		T187	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	1		T9	2		T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	12		T145	1		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T139	16		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T61	1		T145	9		T138	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T12	1		T15	23		T17	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T171	14		T163	12		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T52	12		T81	14		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T26	1		T28	2		T308	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T70	4		T81	8		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T230	6		T156	3		T183	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T238	11		T268	7		T319	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T166	16		T316	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T148	16		T152	12		T294	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T81	3		T106	1		T238	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T171	1		T251	2		T230	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T207	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T141	1		T318	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T141	1		T39	5		T206	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T18	1		T137	12		T70	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T50	1		T208	1		T206	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T210	19		T209	1		T170	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	3		T151	2		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T146	10		T38	14		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T160	1		T147	6		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T70	20		T140	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T9	3		T14	1		T75	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T50	16		T151	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	3		T139	16		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T61	3		T138	12		T173	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	4		T17	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T137	2		T145	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	4		T52	13		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T171	1		T38	2		T26	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T12	1		T15	3		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T146	13		T168	9		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T81	8		T238	14		T268	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T230	6		T337	10		T313	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T207	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T318	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	2		T169	3		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T18	1		T70	6		T148	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	1		T208	13		T252	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T209	8		T170	4		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T16	1		T216	8		T270	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T240	8		T260	1		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T147	2		T153	10		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T70	13		T140	6		T233	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	2		T75	6		T209	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	12		T145	1		T138	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T139	16		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T61	1		T138	16		T165	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T17	13		T53	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	9		T163	12		T199	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T52	12		T193	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T171	14		T26	1		T223	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T15	23		T97	3		T70	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T166	16		T156	3		T215	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T208	14		T141	1		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T18	2		T137	1		T70	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	3		T50	2		T151	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T38	1		T43	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T216	9		T147	3		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T70	14		T146	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T160	1		T174	1		T75	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T140	7		T173	1		T211	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	3		T9	4		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	13		T151	1		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	4		T139	18		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T61	3		T145	10		T138	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T12	3		T15	26		T17	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T137	1		T171	15		T163	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	13		T81	15		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T146	1		T38	1		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T12	1		T19	1		T70	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T146	1		T171	1		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T106	1		T238	12		T268	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T166	17		T239	1		T251	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16309	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T141	1		T148	17		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	4		T286	9		T219	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T137	11		T70	7		T234	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	1		T206	12		T252	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T38	13		T210	18		T240	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T216	9		T147	5		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T70	19		T146	9		T207	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T75	4		T153	11		T218	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T211	17		T233	3		T104	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	1		T9	1		T187	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	15		T138	4		T139	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T139	15		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T61	1		T138	11		T173	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T12	2		T51	14		T64	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T137	1		T199	12		T223	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T52	12		T81	12		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T38	1		T26	1		T165	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T70	5		T81	2		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	11		T168	8		T230	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T238	4		T319	6		T279	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T166	14		T239	10		T316	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T206	12		T231	8		T152	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T148	13		T152	16		T213	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T81	9		T106	1		T238	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T171	1		T251	2		T230	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T207	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T141	1		T318	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T141	1		T39	3		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T18	2		T137	1		T70	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	2		T208	14		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T210	1		T209	9		T170	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	3		T151	2		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T146	1		T38	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T160	1		T147	3		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T70	14		T140	7		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	4		T14	1		T75	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T50	13		T151	1		T145	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	3		T139	17		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T61	3		T138	17		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	4		T17	14		T53	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T137	1		T145	10		T163	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	3		T52	13		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T171	15		T38	1		T26	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T12	1		T15	26		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T146	2		T168	1		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T81	2		T238	7		T279	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T230	7		T313	1		T316	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T318	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	4		T206	12		T231	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T137	11		T70	7		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T206	12		T252	15		T267	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T210	18		T170	1		T261	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	1		T216	9		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T146	9		T38	13		T240	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T147	5		T164	12		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T70	19		T233	3		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T9	1		T75	4		T187	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T50	15		T138	4		T139	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T139	15		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	1		T138	11		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T62	2		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T137	1		T199	12		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	2		T52	12		T168	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	1		T26	1		T223	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T51	14		T64	18		T70	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	11		T168	8		T165	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2