Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21837

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3189

1

T7

4

T9

5

T12

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19138

1

T1

20

T4

10

T5

20

auto[1]

5888

1

T9

5

T14

1

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	76	1			T138	28		T259	10		T262	25
values[0]	78	1			T231	18		T234	7		T338	1
values[1]	655	1			T9	5		T70	10		T160	1
values[2]	732	1			T144	5		T138	11		T173	12
values[3]	652	1			T12	1		T50	30		T137	2
values[4]	662	1			T18	2		T53	13		T81	27
values[5]	2828	1			T13	5		T14	1		T15	26
values[6]	557	1			T12	5		T151	1		T160	1
values[7]	691	1			T7	4		T137	12		T151	1
values[8]	704	1			T19	1		T146	1		T171	15
values[9]	1160	1			T16	4		T17	14		T52	25
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	910	1			T9	5		T70	10		T160	1
values[1]	814	1			T12	1		T81	11		T138	11
values[2]	532	1			T50	30		T137	2		T139	32
values[3]	2935	1			T14	1		T15	26		T18	2
values[4]	518	1			T13	5		T53	13		T151	1
values[5]	711	1			T7	4		T12	5		T151	1
values[6]	530	1			T19	1		T151	1		T62	7
values[7]	856	1			T61	4		T137	12		T208	14
values[8]	657	1			T16	4		T70	47		T145	10
values[9]	310	1			T17	14		T52	25		T138	28
minimum	16253	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T70	6		T160	1		T139	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	3		T144	3		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	1		T81	3		T148	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T138	5		T146	12		T206	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	1		T137	2		T164	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T50	16		T139	16		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T15	3		T51	15		T64	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	1		T18	1		T81	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	1		T173	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	4		T53	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T151	1		T160	1		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	3		T12	4		T211	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	1		T62	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T19	1		T141	1		T250	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T137	12		T208	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T61	3		T146	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	3		T70	28		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T145	1		T38	14		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T171	1		T40	1		T229	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T17	1		T52	13		T138	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16141	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T339	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T70	4		T163	12		T147	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	2		T144	2		T187	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T81	8		T148	16		T47	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	6		T223	12		T233	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T50	1		T170	4		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T50	12		T139	16		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T15	23		T97	3		T161	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	1		T81	14		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T145	3		T170	1		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	1		T53	12		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T147	10		T199	12		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T12	1		T75	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T62	2		T140	6		T165	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T47	6		T153	10		T238	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T208	13		T171	14		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	1		T209	13		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	1		T70	19		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	9		T214	14		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T171	5		T229	10		T237	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T17	13		T52	12		T138	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T339	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T262	21		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T138	12		T259	7		T280	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T231	9		T234	7		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T337	1		T340	14		T341	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T70	6		T160	1		T139	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	3		T63	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T173	12		T164	13		T148	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T144	3		T138	5		T206	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T50	1		T137	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T50	16		T139	16		T146	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T145	1		T171	1		T216	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T18	1		T53	1		T81	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T15	3		T51	15		T64	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	4		T14	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T151	1		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	4		T39	5		T211	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T137	12		T151	1		T62	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	3		T250	2		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T171	1		T140	1		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T19	1		T146	1		T141	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T16	3		T70	28		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T17	1		T52	13		T61	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T262	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T138	16		T259	3		T280	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T231	9		T238	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T337	1		T340	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T70	4		T163	12		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	2		T187	3		T226	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T148	16		T47	9		T255	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T144	2		T138	6		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T50	1		T81	8		T170	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	12		T139	16		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T145	1		T216	8		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	1		T53	12		T81	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T15	23		T97	3		T161	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	1		T41	6		T71	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T152	12		T232	10		T183	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T39	2		T265	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T62	2		T147	10		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	1		T209	8		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T171	14		T140	6		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T209	13		T47	6		T207	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T16	1		T70	19		T208	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T17	13		T52	12		T61	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T70	5		T160	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	4		T144	3		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T81	9		T148	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	7		T146	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T50	2		T137	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	13		T139	17		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T15	26		T51	1		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T18	2		T81	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T145	4		T173	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	4		T53	13		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T151	1		T160	1		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	3		T12	3		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T151	1		T62	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	1		T141	1		T250	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T137	1		T208	14		T171	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T61	3		T146	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	3		T70	21		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T145	10		T38	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T171	6		T40	1		T229	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T17	14		T52	13		T138	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16248	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T339	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T70	5		T139	7		T173	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T144	2		T210	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T81	2		T148	13		T211	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T138	4		T146	11		T206	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T137	1		T164	12		T170	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	15		T139	15		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T51	14		T64	18		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T81	12		T144	9		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T261	3		T156	9		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T13	1		T39	4		T71	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T147	11		T38	12		T199	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	1		T12	2		T211	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T62	2		T168	7		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T153	11		T238	14		T226	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T137	11		T168	12		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T61	1		T173	11		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	1		T70	26		T263	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T38	13		T165	8		T261	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T229	8		T156	10		T227	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T52	12		T138	11		T168	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T339	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T262	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T138	17		T259	8		T280	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T231	10		T234	1		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T337	2		T340	14		T341	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T70	5		T160	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	4		T63	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T173	1		T164	1		T148	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T144	3		T138	7		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	1		T50	2		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T50	13		T139	17		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T145	2		T171	1		T216	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T18	2		T53	13		T81	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T15	26		T51	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	4		T14	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T151	1		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	3		T39	3		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T137	1		T151	1		T62	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	3		T250	2		T209	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T171	15		T140	7		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	1		T146	1		T141	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T16	3		T70	21		T208	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T17	14		T52	13		T61	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T262	20		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T138	11		T259	2		T280	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T231	8		T234	6		T238	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T340	13		T341	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T70	5		T139	7		T147	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T9	1		T187	5		T226	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T173	11		T164	12		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T144	2		T138	4		T206	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T137	1		T81	2		T170	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	15		T139	15		T146	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T216	9		T252	11		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T81	12		T144	9		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T51	14		T64	18		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	1		T71	13		T75	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	12		T210	4		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	2		T39	4		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	11		T62	2		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	1		T238	14		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T168	19		T26	1		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T173	11		T223	14		T207	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	1		T70	26		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T52	12		T61	1		T168	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2