Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21858

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3168

1

T7

4

T9

5

T12

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19126

1

T1

20

T4

10

T5

20

auto[1]

5900

1

T9

5

T14

1

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T16	4		T28	9		T156	13
values[0]	52	1			T234	7		T238	16		T337	2
values[1]	727	1			T9	5		T70	10		T160	1
values[2]	675	1			T12	1		T138	11		T146	12
values[3]	715	1			T50	30		T137	2		T81	11
values[4]	597	1			T18	2		T81	27		T144	12
values[5]	2843	1			T13	5		T14	1		T15	26
values[6]	557	1			T7	4		T12	5		T151	1
values[7]	677	1			T19	1		T151	1		T62	7
values[8]	775	1			T137	12		T146	1		T171	15
values[9]	963	1			T17	14		T52	25		T61	4
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	639	1			T9	5		T160	1		T144	5
values[1]	755	1			T12	1		T81	11		T138	11
values[2]	601	1			T50	30		T137	2		T139	32
values[3]	2859	1			T14	1		T15	26		T18	2
values[4]	595	1			T13	5		T53	13		T151	1
values[5]	651	1			T7	4		T12	5		T151	1
values[6]	570	1			T19	1		T151	1		T62	7
values[7]	866	1			T61	4		T137	12		T208	14
values[8]	763	1			T16	4		T17	14		T70	47
values[9]	213	1			T52	25		T138	28		T171	6
minimum	16514	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T160	1		T163	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	3		T144	3		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T81	3		T148	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T138	5		T146	12		T206	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T50	1		T137	2		T164	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T50	16		T139	16		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T15	3		T51	15		T64	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	1		T18	1		T81	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T145	1		T43	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	4		T53	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T151	1		T160	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	3		T12	4		T211	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T151	1		T62	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	1		T141	1		T250	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T137	12		T208	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T61	3		T146	1		T173	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	3		T70	28		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	1		T141	1		T168	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T171	1		T156	11		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T52	13		T138	12		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16219	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T169	1		T187	6		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T163	12		T207	8		T255	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	2		T144	2		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T81	8		T148	16		T47	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	6		T223	12		T233	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T50	1		T170	4		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T50	12		T139	16		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T15	23		T97	3		T161	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	1		T81	14		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T145	3		T170	1		T156	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	1		T53	12		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	10		T199	12		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T12	1		T75	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T62	2		T140	6		T165	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T47	6		T104	22		T238	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T208	13		T171	14		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T61	1		T209	13		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	1		T70	19		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	13		T187	1		T214	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T171	5		T156	2		T258	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T52	12		T138	16		T219	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T187	3		T226	9		T337	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T16	3		T156	11		T215	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T28	7		T219	14		T259	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T234	7		T238	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T337	1		T340	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T70	6		T160	1		T139	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	3		T144	3		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	1		T141	1		T173	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T138	5		T146	12		T206	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	1		T137	2		T81	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T50	16		T139	16		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T145	1		T171	1		T216	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	1		T81	13		T144	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T15	3		T51	15		T64	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	4		T14	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T151	1		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	3		T12	4		T39	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T151	1		T62	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	1		T250	2		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T137	12		T171	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T146	1		T141	2		T173	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T70	28		T208	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T17	1		T52	13		T61	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T16	1		T156	2		T215	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T28	2		T219	5		T259	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T238	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T337	1		T340	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T70	4		T163	12		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	2		T144	2		T187	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T148	16		T47	9		T222	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T138	6		T223	12		T233	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T50	1		T81	8		T170	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	12		T139	16		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T145	1		T216	8		T291	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	1		T81	14		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T15	23		T97	3		T161	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	1		T53	12		T41	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T199	12		T231	11		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	1		T12	1		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T62	2		T147	10		T187	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T209	8		T222	2		T104	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T171	14		T140	6		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T209	13		T47	6		T207	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T70	19		T208	13		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	13		T52	12		T61	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T160	1		T163	13		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	4		T144	3		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T81	9		T148	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	7		T146	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T50	2		T137	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T50	13		T139	17		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T15	26		T51	1		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T18	2		T81	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T145	4		T43	1		T170	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	4		T53	13		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T151	1		T160	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	3		T12	3		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	1		T62	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T19	1		T141	1		T250	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T137	1		T208	14		T171	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T61	3		T146	1		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	3		T70	21		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T17	14		T141	1		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T171	6		T156	3		T258	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T52	13		T138	17		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16329	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T169	1		T187	4		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T173	11		T207	7		T234	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	1		T144	2		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T81	2		T148	13		T211	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	4		T146	11		T206	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T137	1		T164	12		T170	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T50	15		T139	15		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T51	14		T64	18		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T81	12		T144	9		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T261	13		T156	9		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	1		T39	4		T71	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T147	11		T38	12		T199	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	1		T12	2		T211	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	2		T168	7		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T104	21		T238	14		T226	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T137	11		T168	12		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T61	1		T173	11		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	1		T70	26		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T168	8		T38	13		T165	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T156	10		T189	1		T227	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T52	12		T138	11		T219	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T70	5		T139	7		T147	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T187	5		T226	12		T340	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T16	3		T156	3		T215	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T28	7		T219	6		T259	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T234	1		T238	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T337	2		T340	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T70	5		T160	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	4		T144	3		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T141	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T138	7		T146	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	2		T137	1		T81	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	13		T139	17		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T145	2		T171	1		T216	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	2		T81	15		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T15	26		T51	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	4		T14	1		T53	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	1		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	3		T12	3		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T151	1		T62	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T19	1		T250	2		T209	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	1		T171	15		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T146	1		T141	2		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T70	21		T208	14		T145	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T17	14		T52	13		T61	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	1		T156	10		T215	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T28	2		T219	13		T259	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T234	6		T238	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T340	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T70	5		T139	7		T147	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	1		T144	2		T187	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T173	11		T148	13		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	4		T146	11		T206	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T137	1		T81	2		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T50	15		T139	15		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T216	9		T237	10		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T81	12		T144	9		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T51	14		T64	18		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	1		T71	13		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T38	12		T199	12		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T7	1		T12	2		T39	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T62	2		T147	11		T168	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T104	21		T238	14		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T137	11		T168	12		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T173	11		T223	14		T207	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T70	26		T38	1		T165	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T52	12		T61	1		T138	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2