Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21719

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3307

1

T9

5

T13

5

T16

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18745

1

T1

20

T4

10

T5

20

auto[1]

6281

1

T9

5

T12

5

T14

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T61	4		T137	2		T62	7
values[0]	66	1			T139	1		T146	12		T261	14
values[1]	863	1			T16	4		T17	14		T53	13
values[2]	2791	1			T12	1		T15	26		T51	15
values[3]	631	1			T70	33		T208	14		T81	27
values[4]	700	1			T9	5		T50	28		T139	32
values[5]	585	1			T7	4		T12	5		T13	5
values[6]	743	1			T138	11		T164	13		T38	27
values[7]	684	1			T18	2		T52	25		T137	12
values[8]	683	1			T19	1		T160	1		T171	1
values[9]	812	1			T151	1		T171	21		T141	1
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T16	4		T17	14		T53	13
values[1]	2893	1			T12	1		T15	26		T51	15
values[2]	489	1			T208	14		T81	27		T146	1
values[3]	800	1			T9	5		T12	5		T50	28
values[4]	604	1			T7	4		T13	5		T14	1
values[5]	811	1			T18	2		T52	25		T81	11
values[6]	590	1			T137	12		T160	1		T171	1
values[7]	762	1			T19	1		T140	7		T141	1
values[8]	739	1			T61	4		T137	2		T151	1
values[9]	64	1			T171	6		T210	11		T170	2
minimum	16476	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T70	6		T167	1		T71	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	3		T17	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T12	1		T15	3		T51	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T70	20		T151	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T146	1		T63	1		T249	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T208	1		T81	13		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	4		T50	16		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	3		T40	1		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	3		T14	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	4		T145	1		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T18	1		T52	13		T81	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T164	13		T174	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T142	1		T165	3		T233	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T137	12		T160	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T173	13		T229	9		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T19	1		T140	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T61	3		T137	2		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T151	1		T62	5		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T171	1		T177	1		T294	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T210	11		T170	1		T296	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16193	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T145	1		T139	1		T166	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T70	4		T71	13		T187	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	1		T17	13		T53	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T15	23		T97	3		T161	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T70	13		T145	3		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	12		T104	10		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T208	13		T81	14		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T50	12		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	2		T231	20		T207	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	1		T50	1		T70	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	1		T145	9		T138	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	1		T52	12		T81	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T222	2		T238	17		T258	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T165	7		T233	4		T187	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T223	2		T270	15		T253	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T229	10		T169	5		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T140	6		T165	3		T255	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T61	1		T171	14		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T62	2		T199	12		T47	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T171	5		T294	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T170	1		T297	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T145	1		T166	16		T209	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T61	3		T137	2		T147	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T62	5		T199	13		T234	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T146	12		T261	14		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T139	1		T342	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T167	1		T71	14		T187	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	3		T17	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T12	1		T15	3		T51	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T151	1		T145	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	1		T63	1		T249	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T70	20		T208	1		T81	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	16		T139	16		T216	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	3		T147	12		T206	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	3		T12	4		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	4		T145	1		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T138	5		T38	14		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T164	13		T38	13		T165	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T18	1		T52	13		T81	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T137	12		T43	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T173	13		T169	1		T275	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T19	1		T160	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T171	2		T141	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T151	1		T188	1		T210	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T61	1		T147	2		T207	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T62	2		T199	12		T293	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T281	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T342	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T71	13		T187	3		T222	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	1		T17	13		T53	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T15	23		T97	3		T70	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T145	3		T163	12		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	12		T104	10		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	13		T208	13		T81	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T50	12		T139	16		T216	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	2		T147	10		T231	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T12	1		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	1		T145	9		T138	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T138	6		T169	3		T209	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T265	13		T222	2		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T18	1		T52	12		T81	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T223	2		T238	14		T270	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T169	5		T178	8		T221	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T140	6		T165	3		T255	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T171	19		T41	6		T223	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	6		T170	1		T207	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T70	5		T167	1		T71	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	3		T17	14		T53	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T12	1		T15	26		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T70	14		T151	1		T145	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	1		T63	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T208	14		T81	15		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	3		T50	13		T139	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	4		T40	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	3		T14	1		T50	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	4		T145	10		T138	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	2		T52	13		T81	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T164	1		T174	1		T222	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T142	1		T165	8		T233	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T137	1		T160	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T173	2		T229	11		T169	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T19	1		T140	7		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T61	3		T137	1		T171	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T151	1		T62	5		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T171	6		T177	1		T294	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T210	1		T170	2		T296	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16302	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T145	2		T139	1		T166	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T70	5		T71	13		T187	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	1		T139	7		T168	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T51	14		T64	18		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T70	19		T26	1		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T249	2		T152	16		T104	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T81	12		T147	11		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	2		T50	15		T139	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T206	12		T231	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	1		T70	7		T138	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	1		T138	11		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T52	12		T81	2		T148	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T164	12		T263	6		T238	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T165	2		T233	3		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T137	11		T223	12		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T173	11		T229	8		T275	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T165	12		T255	12		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T61	1		T137	1		T147	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T62	2		T210	4		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T294	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T210	10		T297	9		T271	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T146	11		T261	13		T343	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T166	14		T277	13		T280	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T61	3		T137	1		T147	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T62	5		T199	13		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T146	1		T261	1		T281	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T139	1		T342	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T167	1		T71	14		T187	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T16	3		T17	14		T53	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T12	1		T15	26		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	1		T145	4		T163	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T146	1		T63	1		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T70	14		T208	14		T81	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	13		T139	17		T216	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T147	11		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	3		T12	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	4		T145	10		T138	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T138	7		T38	1		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T164	1		T38	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T18	2		T52	13		T81	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T137	1		T43	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T173	2		T169	6		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T19	1		T160	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T171	21		T141	1		T41	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T151	1		T188	1		T210	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T61	1		T137	1		T147	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T62	2		T199	12		T234	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T146	11		T261	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T342	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T71	13		T187	5		T237	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	1		T139	7		T168	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T51	14		T64	18		T70	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T26	1		T211	10		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T249	2		T152	16		T104	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T70	19		T81	12		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	15		T139	15		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	1		T147	11		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	1		T12	2		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	1		T138	11		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T138	4		T38	13		T206	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T164	12		T38	12		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	12		T81	2		T148	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T137	11		T223	12		T245	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T173	11		T275	12		T178	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T165	12		T255	12		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T223	12		T229	8		T240	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T210	14		T223	14		T207	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2