Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T138	12		T246	1		T247	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T32	3		T248	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T63	1		T168	8		T229	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T208	1		T147	12		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T70	20		T146	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T139	8		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	1		T16	3		T81	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T13	4		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T138	5		T38	2		T39	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	1		T137	2		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T151	1		T145	1		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T160	1		T141	1		T168	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T70	8		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	3		T144	3		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	4		T52	13		T81	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	3		T50	16		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T15	3		T17	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	1		T141	1		T216	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T151	1		T144	10		T173	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	433	1			T70	6		T146	12		T173	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T138	16		T247	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T32	1		T248	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T229	10		T47	6		T207	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T208	13		T147	10		T170	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T70	13		T163	12		T140	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T245	9		T258	13		T259	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	1		T81	8		T145	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	1		T165	3		T75	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	6		T39	2		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	1		T145	3		T62	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T145	9		T28	2		T230	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T142	6		T166	16		T47	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T70	6		T148	16		T71	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	2		T144	2		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T52	12		T81	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	1		T50	12		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T15	23		T17	13		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T53	12		T216	8		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T144	2		T252	7		T260	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T70	4		T199	12		T170	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T70	14		T63	1		T168	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T208	14		T174	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T140	7		T210	1		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T141	1		T147	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	1		T16	3		T81	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	4		T145	4		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T145	10		T138	7		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T18	2		T137	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T151	1		T160	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T160	1		T144	3		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T70	7		T38	1		T41	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T171	6		T250	2		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T12	3		T15	26		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	3		T9	4		T50	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	14		T50	2		T61	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T53	13		T216	9		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T151	1		T144	3		T252	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T70	5		T138	17		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T249	1		T253	2		T215	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T152	13		T246	1		T254	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T152	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T70	19		T168	15		T229	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T170	1		T261	3		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T210	18		T223	14		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T147	11		T75	4		T187	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	1		T81	2		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T139	7		T147	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T138	4		T39	4		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T137	1		T62	2		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T148	13		T38	12		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T144	2		T168	12		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T70	7		T38	13		T71	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T255	12		T261	10		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T12	2		T51	14		T52	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	1		T9	1		T50	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T61	1		T146	9		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T216	9		T26	1		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T144	9		T252	15		T263	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T70	5		T138	11		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T249	2		T215	4		T242	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T152	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T138	17		T246	1		T247	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T32	3		T248	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T63	1		T168	1		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T208	14		T147	11		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T70	14		T146	1		T163	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T139	1		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T16	3		T81	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T13	4		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T138	7		T38	1		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T18	2		T137	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	1		T145	10		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T160	1		T141	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T70	7		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	4		T144	3		T171	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	3		T52	13		T81	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	3		T50	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T15	26		T17	14		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T53	13		T141	1		T216	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T151	1		T144	3		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T70	5		T146	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T138	11		T247	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T32	1		T248	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T168	7		T229	8		T207	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T147	11		T170	1		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T70	19		T168	8		T210	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T139	7		T245	8		T259	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	1		T81	2		T139	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T165	12		T75	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	4		T38	1		T39	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	1		T62	2		T147	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	12		T206	12		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T168	12		T166	14		T210	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T70	7		T148	13		T38	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	1		T144	2		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T52	12		T81	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	1		T50	15		T137	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T51	14		T64	18		T61	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T216	9		T26	1		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T144	9		T173	11		T249	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T70	5		T146	11		T173	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2